AI-driven design automation - Revision history

Copparihollmann: Fixed formatting

2025-06-17T13:19:51Z

Fixed formatting

← Previous revision		Revision as of 13:19, 17 June 2025
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	<ref name="Rapp2021MLCAD">{{Cite journal \|last=Rapp \|first=Martin \|last2=Amrouch \|first2=Hussam \|last3=Lin \|first3=Yibo \|last4=Yu \|first4=Bei \|last5=Pan \|first5=David Z. \|last6=Wolf \|first6=Marilyn \|last7=Henkel \|first7=Jörg \|date=October 2022 \|title=MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper \|url=https://ieeexplore.ieee.org/abstract/document/9598835 \|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems \|volume=41 \|issue=10 \|pages=3162–3181 \|doi=10.1109/TCAD.2021.3124762 \|issn=1937-4151}}</ref>		<ref name="Rapp2021MLCAD">{{Cite journal \|last=Rapp \|first=Martin \|last2=Amrouch \|first2=Hussam \|last3=Lin \|first3=Yibo \|last4=Yu \|first4=Bei \|last5=Pan \|first5=David Z. \|last6=Wolf \|first6=Marilyn \|last7=Henkel \|first7=Jörg \|date=October 2022 \|title=MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper \|url=https://ieeexplore.ieee.org/abstract/document/9598835 \|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems \|volume=41 \|issue=10 \|pages=3162–3181 \|doi=10.1109/TCAD.2021.3124762 \|issn=1937-4151}}</ref>
	<ref name="Gubbi2022Survey">{{Cite journal \|last=Gubbi \|first=Kevin Immanuel \|last2=Beheshti-Shirazi \|first2=Sayed Aresh \|last3=Sheaves \|first3=Tyler \|last4=Salehi \|first4=Soheil \|last5=PD \|first5=Sai Manoj \|last6=Rafatirad \|first6=Setareh \|last7=Sasan \|first7=Avesta \|last8=Homayoun \|first8=Houman \|date=2022-06-06 \|title=Survey of Machine Learning for Electronic Design Automation \|url=https://dl.acm.org/doi/10.1145/3526241.3530834 \|journal=Proceedings of the Great Lakes Symposium on VLSI 2022 \|series=GLSVLSI '22 \|location=New York, NY, USA \|publisher=Association for Computing Machinery \|pages=513–518 \|doi=10.1145/3526241.3530834 \|isbn=978-1-4503-9322-5}}</ref>		<ref name="Gubbi2022Survey">{{Cite journal \|last=Gubbi \|first=Kevin Immanuel \|last2=Beheshti-Shirazi \|first2=Sayed Aresh \|last3=Sheaves \|first3=Tyler \|last4=Salehi \|first4=Soheil \|last5=PD \|first5=Sai Manoj \|last6=Rafatirad \|first6=Setareh \|last7=Sasan \|first7=Avesta \|last8=Homayoun \|first8=Houman \|date=2022-06-06 \|title=Survey of Machine Learning for Electronic Design Automation \|url=https://dl.acm.org/doi/10.1145/3526241.3530834 \|journal=Proceedings of the Great Lakes Symposium on VLSI 2022 \|series=GLSVLSI '22 \|location=New York, NY, USA \|publisher=Association for Computing Machinery \|pages=513–518 \|doi=10.1145/3526241.3530834 \|isbn=978-1-4503-9322-5}}</ref>
	<ref name="Chen2024AINativeEDA">{{cite arxiv \|last1=Chen \|first1=L. \|last2=Chen \|first2=Y. \|last3=Chu \|first3=Z. \|last4=Fang \|first4=W. \|last5=Ho \|first5=T. Y. \|last6=Huang \|first6=R. \|year=2024 \|title=The dawn of ai-native eda: Opportunities and challenges of large circuit models \|eprint=2403.07257}}</ref>
	<ref name="CadenceAIOverview">{{cite web \|url=https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/transforming-chip-design-with-agentic-ai-introducing-cadence-cerebrus-ai-studio \|title=Cadence.AI: Transforming Chip Design with Agentic AI Workflows \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>		<ref name="CadenceAIOverview">{{cite web \|url=https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/transforming-chip-design-with-agentic-ai-introducing-cadence-cerebrus-ai-studio \|title=Cadence.AI: Transforming Chip Design with Agentic AI Workflows \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>
	<ref name="CadenceEDAWhatIs">{{cite web \|url=https://www.cadence.com/en_US/home/explore/what-is-electronic-design-automation.html#:~:text=Electronic%20design%20automation%20(EDA)%20is,hand%20and%20utilized%20siloed%20tools. \|title=What is Electronic Design Automation (EDA)? \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>		<ref name="CadenceEDAWhatIs">{{cite web \|url=https://www.cadence.com/en_US/home/explore/what-is-electronic-design-automation.html#:~:text=Electronic%20design%20automation%20(EDA)%20is,hand%20and%20utilized%20siloed%20tools. \|title=What is Electronic Design Automation (EDA)? \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>

Copparihollmann: Refined citation

2025-06-17T13:18:38Z

Refined citation

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Copparihollmann: Adjusted size of images.

2025-06-17T13:07:31Z

Adjusted size of images.

← Previous revision		Revision as of 13:07, 17 June 2025
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	'''AI Driven Design Automation''' is the use of [[artificial intelligence]] (AI) to automate and improve different parts of the [[electronic design automation]] (EDA) process. This applies especially to designing [[integrated circuit]]s (chips) and complex electronic systems. This field has become important because it can help solve the growing problems of complexity, high costs, and the need to release products faster in the [[semiconductor industry]]. AI Driven Design Automation uses several methods, including [[machine learning]], [[expert system]]s, and [[reinforcement learning]]. These are used for many tasks, from planning a chip's architecture and [[logic synthesis]] to its [[physical design (electronics)\|physical design]] and final [[verification and validation\|verification]].		'''AI Driven Design Automation''' is the use of [[artificial intelligence]] (AI) to automate and improve different parts of the [[electronic design automation]] (EDA) process. This applies especially to designing [[integrated circuit]]s (chips) and complex electronic systems. This field has become important because it can help solve the growing problems of complexity, high costs, and the need to release products faster in the [[semiconductor industry]]. AI Driven Design Automation uses several methods, including [[machine learning]], [[expert system]]s, and [[reinforcement learning]]. These are used for many tasks, from planning a chip's architecture and [[logic synthesis]] to its [[physical design (electronics)\|physical design]] and final [[verification and validation\|verification]].
	[[File:EDA Large Circuit Models.png\|thumb\|This figure explains how can we train large circuit models by making use of the front-end (depicted in blue) and back-end (depicted in yellow) of the EDA flow in order to either enhance existing EDA tools or to create novel EDA applications.<ref name=":0">{{Citation \|last=Chen \|first=Lei \|title=The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models \|date=2024-05-01 \|url=http://arxiv.org/abs/2403.07257 \|access-date=2025-06-14 \|publisher=arXiv \|doi=10.48550/arXiv.2403.07257 \|id=arXiv:2403.07257 \|last2=Chen \|first2=Yiqi \|last3=Chu \|first3=Zhufei \|last4=Fang \|first4=Wenji \|last5=Ho \|first5=Tsung-Yi \|last6=Huang \|first6=Ru \|last7=Huang \|first7=Yu \|last8=Khan \|first8=Sadaf \|last9=Li \|first9=Min}}</ref>\|~~594x594px~~]]		[[File:EDA Large Circuit Models.png\|thumb\|This figure explains how can we train large circuit models by making use of the front-end (depicted in blue) and back-end (depicted in yellow) of the EDA flow in order to either enhance existing EDA tools or to create novel EDA applications.<ref name=":0">{{Citation \|last=Chen \|first=Lei \|title=The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models \|date=2024-05-01 \|url=http://arxiv.org/abs/2403.07257 \|access-date=2025-06-14 \|publisher=arXiv \|doi=10.48550/arXiv.2403.07257 \|id=arXiv:2403.07257 \|last2=Chen \|first2=Yiqi \|last3=Chu \|first3=Zhufei \|last4=Fang \|first4=Wenji \|last5=Ho \|first5=Tsung-Yi \|last6=Huang \|first6=Ru \|last7=Huang \|first7=Yu \|last8=Khan \|first8=Sadaf \|last9=Li \|first9=Min}}</ref>\|453x453px]]

	==History==		==History==
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	====Placement====		====Placement====
	[[Place and route#Placement\|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller [[Standard cell\|standard cells]]. [[Reinforcement learning]] has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing<ref name="Mirhoseini2021Floorplanning" /> and other examples like the GoodFloorplan method.<ref name="Xu2021GoodFloorplan" /> Supervised learning models, including [[Convolutional neural network\|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking\|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet" />) or timing after routing directly from the [[Placement (electronic design automation)\|placement]] information.<ref name="Rapp2021MLCAD" /><ref name=":0" /> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer" />		[[Place and route#Placement\|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller [[Standard cell\|standard cells]]. [[Reinforcement learning]] has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing<ref name="Mirhoseini2021Floorplanning" /> and other examples like the GoodFloorplan method.<ref name="Xu2021GoodFloorplan" /> Supervised learning models, including [[Convolutional neural network\|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking\|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet" />) or timing after routing directly from the [[Placement (electronic design automation)\|placement]] information.<ref name="Rapp2021MLCAD" /><ref name=":0" /> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer" />
	[[File:Complexity Comparison Floorplanning.png\|thumb\|Complexity of board games compared to floorplanning in chip design: chess is estimated to have a complexity of ≈ 10¹²⁶, Go about 10³⁶⁰, while arranging hundreds of hard macros on a silicon die balloons beyond 10²⁵⁰⁰ possibilities. The arrow highlights this steep rise in combinatorial complexity.<ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref><ref>{{Cite AV media \|url=https://www.youtube.com/watch?v=zR9IusOpEzk \|title=Google’s Chip Designing AI \|date=2021-12-12 \|last=Asianometry \|access-date=2025-06-17 \|via=YouTube}}</ref>\|~~494x494px~~]]		[[File:Complexity Comparison Floorplanning.png\|thumb\|Complexity of board games compared to floorplanning in chip design: chess is estimated to have a complexity of ≈ 10¹²⁶, Go about 10³⁶⁰, while arranging hundreds of hard macros on a silicon die balloons beyond 10²⁵⁰⁰ possibilities. The arrow highlights this steep rise in combinatorial complexity.<ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref><ref>{{Cite AV media \|url=https://www.youtube.com/watch?v=zR9IusOpEzk \|title=Google’s Chip Designing AI \|date=2021-12-12 \|last=Asianometry \|access-date=2025-06-17 \|via=YouTube}}</ref>\|441x441px]]

	====Clock network synthesis====		====Clock network synthesis====
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	In EDA, RL is especially good for tasks that require making a series of decisions to find the best solution in very complex situations with many variables. Its adoption by commercial EDA products shows its growing importance.<ref name="SynopsysAI2023"/> RL has been used for physical design problems like chip [[Floorplan (microelectronics)\|floorplanning]]. In this task, an agent learns to place blocks to improve things like wire length and performance.<ref name="Mirhoseini2021Floorplanning"/><ref name="Xu2021GoodFloorplan"/> In logic synthesis, RL can guide how optimization steps are chosen and in what order they are applied to get better results, as seen in methods like AlphaSyn.<ref name="Pei2023AlphaSyn"/> Another example where RL agents can learn effective strategies is adjusting the size of gates to optimize timing.<ref name="Lu2021RLSizer"/>		In EDA, RL is especially good for tasks that require making a series of decisions to find the best solution in very complex situations with many variables. Its adoption by commercial EDA products shows its growing importance.<ref name="SynopsysAI2023"/> RL has been used for physical design problems like chip [[Floorplan (microelectronics)\|floorplanning]]. In this task, an agent learns to place blocks to improve things like wire length and performance.<ref name="Mirhoseini2021Floorplanning"/><ref name="Xu2021GoodFloorplan"/> In logic synthesis, RL can guide how optimization steps are chosen and in what order they are applied to get better results, as seen in methods like AlphaSyn.<ref name="Pei2023AlphaSyn"/> Another example where RL agents can learn effective strategies is adjusting the size of gates to optimize timing.<ref name="Lu2021RLSizer"/>
	[[File:Floorplanning comparison.png\|thumb\|~~427x427px~~\|Comparison of macro-placement strategies for a system-on-chip floorplan: a handcrafted layout created by a human designer (left) and a layout generated by an AI-assisted placer (right). The AI approach combines explicit design-rule constraints with heuristic search and reinforcement-learning optimization, allowing it to evaluate placements that are not obvious to humans while still meeting power, performance and area targets.<ref>{{Cite web \|last=Attar \|first=Janet \|date=2024-01-11 \|title=AI-Driven Macro Placement Boosts PPA \|url=https://semiengineering.com/ai-driven-macro-placement-boosts-ppa/ \|access-date=2025-06-17 \|website=Semiconductor Engineering \|language=en-US}}</ref><ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref>]]		[[File:Floorplanning comparison.png\|thumb\|358x358px\|Comparison of macro-placement strategies for a system-on-chip floorplan: a handcrafted layout created by a human designer (left) and a layout generated by an AI-assisted placer (right). The AI approach combines explicit design-rule constraints with heuristic search and reinforcement-learning optimization, allowing it to evaluate placements that are not obvious to humans while still meeting power, performance and area targets.<ref>{{Cite web \|last=Attar \|first=Janet \|date=2024-01-11 \|title=AI-Driven Macro Placement Boosts PPA \|url=https://semiengineering.com/ai-driven-macro-placement-boosts-ppa/ \|access-date=2025-06-17 \|website=Semiconductor Engineering \|language=en-US}}</ref><ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref>]]

	===Generative AI===		===Generative AI===

Copparihollmann: Improved visibility of images and added a new figure for comparison between handcrafted vs AI generated placement of macros.

2025-06-17T12:53:00Z

Improved visibility of images and added a new figure for comparison between handcrafted vs AI generated placement of macros.

← Previous revision		Revision as of 12:53, 17 June 2025
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	'''AI Driven Design Automation''' is the use of [[artificial intelligence]] (AI) to automate and improve different parts of the [[electronic design automation]] (EDA) process. This applies especially to designing [[integrated circuit]]s (chips) and complex electronic systems. This field has become important because it can help solve the growing problems of complexity, high costs, and the need to release products faster in the [[semiconductor industry]]. AI Driven Design Automation uses several methods, including [[machine learning]], [[expert system]]s, and [[reinforcement learning]]. These are used for many tasks, from planning a chip's architecture and [[logic synthesis]] to its [[physical design (electronics)\|physical design]] and final [[verification and validation\|verification]].		'''AI Driven Design Automation''' is the use of [[artificial intelligence]] (AI) to automate and improve different parts of the [[electronic design automation]] (EDA) process. This applies especially to designing [[integrated circuit]]s (chips) and complex electronic systems. This field has become important because it can help solve the growing problems of complexity, high costs, and the need to release products faster in the [[semiconductor industry]]. AI Driven Design Automation uses several methods, including [[machine learning]], [[expert system]]s, and [[reinforcement learning]]. These are used for many tasks, from planning a chip's architecture and [[logic synthesis]] to its [[physical design (electronics)\|physical design]] and final [[verification and validation\|verification]].
	[[File:EDA Large Circuit Models.png\|thumb\|This figure explains how can we train large circuit models by making use of the front-end (depicted in blue) and back-end (depicted in yellow) of the EDA flow in order to either enhance existing EDA tools or to create novel EDA applications.<ref name=":0">{{Citation \|last=Chen \|first=Lei \|title=The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models \|date=2024-05-01 \|url=http://arxiv.org/abs/2403.07257 \|access-date=2025-06-14 \|publisher=arXiv \|doi=10.48550/arXiv.2403.07257 \|id=arXiv:2403.07257 \|last2=Chen \|first2=Yiqi \|last3=Chu \|first3=Zhufei \|last4=Fang \|first4=Wenji \|last5=Ho \|first5=Tsung-Yi \|last6=Huang \|first6=Ru \|last7=Huang \|first7=Yu \|last8=Khan \|first8=Sadaf \|last9=Li \|first9=Min}}</ref>]]		[[File:EDA Large Circuit Models.png\|thumb\|This figure explains how can we train large circuit models by making use of the front-end (depicted in blue) and back-end (depicted in yellow) of the EDA flow in order to either enhance existing EDA tools or to create novel EDA applications.<ref name=":0">{{Citation \|last=Chen \|first=Lei \|title=The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models \|date=2024-05-01 \|url=http://arxiv.org/abs/2403.07257 \|access-date=2025-06-14 \|publisher=arXiv \|doi=10.48550/arXiv.2403.07257 \|id=arXiv:2403.07257 \|last2=Chen \|first2=Yiqi \|last3=Chu \|first3=Zhufei \|last4=Fang \|first4=Wenji \|last5=Ho \|first5=Tsung-Yi \|last6=Huang \|first6=Ru \|last7=Huang \|first7=Yu \|last8=Khan \|first8=Sadaf \|last9=Li \|first9=Min}}</ref>\|594x594px]]

	==History==		==History==
Line 47:		Line 47:
	====Placement====		====Placement====
	[[Place and route#Placement\|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller [[Standard cell\|standard cells]]. [[Reinforcement learning]] has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing<ref name="Mirhoseini2021Floorplanning" /> and other examples like the GoodFloorplan method.<ref name="Xu2021GoodFloorplan" /> Supervised learning models, including [[Convolutional neural network\|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking\|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet" />) or timing after routing directly from the [[Placement (electronic design automation)\|placement]] information.<ref name="Rapp2021MLCAD" /><ref name=":0" /> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer" />		[[Place and route#Placement\|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller [[Standard cell\|standard cells]]. [[Reinforcement learning]] has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing<ref name="Mirhoseini2021Floorplanning" /> and other examples like the GoodFloorplan method.<ref name="Xu2021GoodFloorplan" /> Supervised learning models, including [[Convolutional neural network\|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking\|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet" />) or timing after routing directly from the [[Placement (electronic design automation)\|placement]] information.<ref name="Rapp2021MLCAD" /><ref name=":0" /> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer" />
	[[File:Complexity Comparison Floorplanning.png\|thumb\|Complexity of board games compared to floorplanning in chip design: chess is estimated to have a complexity of ≈ 10¹²⁶, Go about 10³⁶⁰, while arranging hundreds of hard macros on a silicon die balloons beyond 10²⁵⁰⁰ possibilities. The arrow highlights this steep rise in combinatorial complexity.<ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref><ref>{{Cite AV media \|url=https://www.youtube.com/watch?v=zR9IusOpEzk \|title=Google’s Chip Designing AI \|date=2021-12-12 \|last=Asianometry \|access-date=2025-06-17 \|via=YouTube}}</ref>]]		[[File:Complexity Comparison Floorplanning.png\|thumb\|Complexity of board games compared to floorplanning in chip design: chess is estimated to have a complexity of ≈ 10¹²⁶, Go about 10³⁶⁰, while arranging hundreds of hard macros on a silicon die balloons beyond 10²⁵⁰⁰ possibilities. The arrow highlights this steep rise in combinatorial complexity.<ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref><ref>{{Cite AV media \|url=https://www.youtube.com/watch?v=zR9IusOpEzk \|title=Google’s Chip Designing AI \|date=2021-12-12 \|last=Asianometry \|access-date=2025-06-17 \|via=YouTube}}</ref>\|494x494px]]

	====Clock network synthesis====		====Clock network synthesis====
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	In EDA, RL is especially good for tasks that require making a series of decisions to find the best solution in very complex situations with many variables. Its adoption by commercial EDA products shows its growing importance.<ref name="SynopsysAI2023"/> RL has been used for physical design problems like chip [[Floorplan (microelectronics)\|floorplanning]]. In this task, an agent learns to place blocks to improve things like wire length and performance.<ref name="Mirhoseini2021Floorplanning"/><ref name="Xu2021GoodFloorplan"/> In logic synthesis, RL can guide how optimization steps are chosen and in what order they are applied to get better results, as seen in methods like AlphaSyn.<ref name="Pei2023AlphaSyn"/> Another example where RL agents can learn effective strategies is adjusting the size of gates to optimize timing.<ref name="Lu2021RLSizer"/>		In EDA, RL is especially good for tasks that require making a series of decisions to find the best solution in very complex situations with many variables. Its adoption by commercial EDA products shows its growing importance.<ref name="SynopsysAI2023"/> RL has been used for physical design problems like chip [[Floorplan (microelectronics)\|floorplanning]]. In this task, an agent learns to place blocks to improve things like wire length and performance.<ref name="Mirhoseini2021Floorplanning"/><ref name="Xu2021GoodFloorplan"/> In logic synthesis, RL can guide how optimization steps are chosen and in what order they are applied to get better results, as seen in methods like AlphaSyn.<ref name="Pei2023AlphaSyn"/> Another example where RL agents can learn effective strategies is adjusting the size of gates to optimize timing.<ref name="Lu2021RLSizer"/>
			[[File:Floorplanning comparison.png\|thumb\|427x427px\|Comparison of macro-placement strategies for a system-on-chip floorplan: a handcrafted layout created by a human designer (left) and a layout generated by an AI-assisted placer (right). The AI approach combines explicit design-rule constraints with heuristic search and reinforcement-learning optimization, allowing it to evaluate placements that are not obvious to humans while still meeting power, performance and area targets.<ref>{{Cite web \|last=Attar \|first=Janet \|date=2024-01-11 \|title=AI-Driven Macro Placement Boosts PPA \|url=https://semiengineering.com/ai-driven-macro-placement-boosts-ppa/ \|access-date=2025-06-17 \|website=Semiconductor Engineering \|language=en-US}}</ref><ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref>]]

	===Generative AI===		===Generative AI===

Copparihollmann: Added image to exemplify complexity of floorplanning.

2025-06-17T12:41:00Z

Added image to exemplify complexity of floorplanning.

← Previous revision		Revision as of 12:41, 17 June 2025
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	====Placement====		====Placement====
	[[Place and route#Placement\|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller [[Standard cell\|standard cells]]. [[Reinforcement learning]] has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing<ref name="Mirhoseini2021Floorplanning" /> and other examples like the GoodFloorplan method.<ref name="Xu2021GoodFloorplan" /> Supervised learning models, including [[Convolutional neural network\|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking\|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet" />) or timing after routing directly from the [[Placement (electronic design automation)\|placement]] information.<ref name="Rapp2021MLCAD" /><ref name=":0" /> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer" />		[[Place and route#Placement\|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller [[Standard cell\|standard cells]]. [[Reinforcement learning]] has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing<ref name="Mirhoseini2021Floorplanning" /> and other examples like the GoodFloorplan method.<ref name="Xu2021GoodFloorplan" /> Supervised learning models, including [[Convolutional neural network\|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking\|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet" />) or timing after routing directly from the [[Placement (electronic design automation)\|placement]] information.<ref name="Rapp2021MLCAD" /><ref name=":0" /> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer" />
			[[File:Complexity Comparison Floorplanning.png\|thumb\|Complexity of board games compared to floorplanning in chip design: chess is estimated to have a complexity of ≈ 10¹²⁶, Go about 10³⁶⁰, while arranging hundreds of hard macros on a silicon die balloons beyond 10²⁵⁰⁰ possibilities. The arrow highlights this steep rise in combinatorial complexity.<ref>{{Cite journal \|last=Mirhoseini \|first=Azalia \|last2=Goldie \|first2=Anna \|last3=Yazgan \|first3=Mustafa \|last4=Jiang \|first4=Joe Wenjie \|last5=Songhori \|first5=Ebrahim \|last6=Wang \|first6=Shen \|last7=Lee \|first7=Young-Joon \|last8=Johnson \|first8=Eric \|last9=Pathak \|first9=Omkar \|last10=Nova \|first10=Azade \|last11=Pak \|first11=Jiwoo \|last12=Tong \|first12=Andy \|last13=Srinivasa \|first13=Kavya \|last14=Hang \|first14=William \|last15=Tuncer \|first15=Emre \|date=June 2021 \|title=A graph placement methodology for fast chip design \|url=https://www.nature.com/articles/s41586-021-03544-w \|journal=Nature \|language=en \|volume=594 \|issue=7862 \|pages=207–212 \|doi=10.1038/s41586-021-03544-w \|issn=1476-4687}}</ref><ref>{{Cite AV media \|url=https://www.youtube.com/watch?v=zR9IusOpEzk \|title=Google’s Chip Designing AI \|date=2021-12-12 \|last=Asianometry \|access-date=2025-06-17 \|via=YouTube}}</ref>]]

	====Clock network synthesis====		====Clock network synthesis====
	AI helps in Clock Tree Synthesis (CTS) by optimizing the network that distributes the clock signal. [[Generative adversarial network\|GANs]], sometimes used with RL (e.g., GAN CTS), are used to predict and improve clock tree structures. The goal is to reduce clock skew and power use.<ref name="Rapp2021MLCAD" /><ref name="Gubbi2022Survey" /><ref name=":0" />		AI helps in Clock Tree Synthesis (CTS) by optimizing the network that distributes the clock signal. [[Generative adversarial network\|GANs]], sometimes used with RL (e.g., GAN CTS), are used to predict and improve clock tree structures. The goal is to reduce clock skew and power use.<ref name="Rapp2021MLCAD" /><ref name="Gubbi2022Survey" /><ref name=":0" />

Copparihollmann: Fixed some citation formatting errors

2025-06-16T08:39:51Z

Fixed some citation formatting errors

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Copparihollmann: Copparihollmann moved page User:Copparihollmann/AI-Driven Design Automation to AI-driven design automation: Move to mainspace

2025-06-16T08:25:49Z

Copparihollmann moved page User:Copparihollmann/AI-Driven Design Automation to AI-driven design automation: Move to mainspace

← Previous revision	Revision as of 08:25, 16 June 2025
(No difference)

Copparihollmann: Quality of life in text and restructuring

2025-06-15T17:45:05Z

Quality of life in text and restructuring

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Copparihollmann: Improved format of citations

2025-06-14T21:03:30Z

Improved format of citations

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Altenmann at 17:58, 7 June 2025

2025-06-07T17:58:05Z

← Previous revision		Revision as of 17:58, 7 June 2025
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	[https://www.dac.com/ Design Automation Conference (DAC)] – Premier academic and industry conference for EDA.		[https://www.dac.com/ Design Automation Conference (DAC)] – Premier academic and industry conference for EDA.

	[[Category:Electronic design automation]]		[[:Category:Electronic design automation]]
	[[Category:~~Applied~~ artificial intelligence]]		[[:Category:Applications of artificial intelligence]]
	[[Category:Semiconductor device fabrication]]		[[:Category:Semiconductor device fabrication]]
	[[Category:Integrated circuits]]		[[:Category:Integrated circuits]]

← Previous revision		Revision as of 13:19, 17 June 2025
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	<ref name="Rapp2021MLCAD">{{Cite journal \|last=Rapp \|first=Martin \|last2=Amrouch \|first2=Hussam \|last3=Lin \|first3=Yibo \|last4=Yu \|first4=Bei \|last5=Pan \|first5=David Z. \|last6=Wolf \|first6=Marilyn \|last7=Henkel \|first7=Jörg \|date=October 2022 \|title=MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper \|url=https://ieeexplore.ieee.org/abstract/document/9598835 \|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems \|volume=41 \|issue=10 \|pages=3162–3181 \|doi=10.1109/TCAD.2021.3124762 \|issn=1937-4151}}</ref>		<ref name="Rapp2021MLCAD">{{Cite journal \|last=Rapp \|first=Martin \|last2=Amrouch \|first2=Hussam \|last3=Lin \|first3=Yibo \|last4=Yu \|first4=Bei \|last5=Pan \|first5=David Z. \|last6=Wolf \|first6=Marilyn \|last7=Henkel \|first7=Jörg \|date=October 2022 \|title=MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper \|url=https://ieeexplore.ieee.org/abstract/document/9598835 \|journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems \|volume=41 \|issue=10 \|pages=3162–3181 \|doi=10.1109/TCAD.2021.3124762 \|issn=1937-4151}}</ref>
	<ref name="Gubbi2022Survey">{{Cite journal \|last=Gubbi \|first=Kevin Immanuel \|last2=Beheshti-Shirazi \|first2=Sayed Aresh \|last3=Sheaves \|first3=Tyler \|last4=Salehi \|first4=Soheil \|last5=PD \|first5=Sai Manoj \|last6=Rafatirad \|first6=Setareh \|last7=Sasan \|first7=Avesta \|last8=Homayoun \|first8=Houman \|date=2022-06-06 \|title=Survey of Machine Learning for Electronic Design Automation \|url=https://dl.acm.org/doi/10.1145/3526241.3530834 \|journal=Proceedings of the Great Lakes Symposium on VLSI 2022 \|series=GLSVLSI '22 \|location=New York, NY, USA \|publisher=Association for Computing Machinery \|pages=513–518 \|doi=10.1145/3526241.3530834 \|isbn=978-1-4503-9322-5}}</ref>		<ref name="Gubbi2022Survey">{{Cite journal \|last=Gubbi \|first=Kevin Immanuel \|last2=Beheshti-Shirazi \|first2=Sayed Aresh \|last3=Sheaves \|first3=Tyler \|last4=Salehi \|first4=Soheil \|last5=PD \|first5=Sai Manoj \|last6=Rafatirad \|first6=Setareh \|last7=Sasan \|first7=Avesta \|last8=Homayoun \|first8=Houman \|date=2022-06-06 \|title=Survey of Machine Learning for Electronic Design Automation \|url=https://dl.acm.org/doi/10.1145/3526241.3530834 \|journal=Proceedings of the Great Lakes Symposium on VLSI 2022 \|series=GLSVLSI '22 \|location=New York, NY, USA \|publisher=Association for Computing Machinery \|pages=513–518 \|doi=10.1145/3526241.3530834 \|isbn=978-1-4503-9322-5}}</ref>
	<ref name="Chen2024AINativeEDA">{{cite arxiv \|last1=Chen \|first1=L. \|last2=Chen \|first2=Y. \|last3=Chu \|first3=Z. \|last4=Fang \|first4=W. \|last5=Ho \|first5=T. Y. \|last6=Huang \|first6=R. \|year=2024 \|title=The dawn of ai-native eda: Opportunities and challenges of large circuit models \|eprint=2403.07257}}</ref>
	<ref name="CadenceAIOverview">{{cite web \|url=https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/transforming-chip-design-with-agentic-ai-introducing-cadence-cerebrus-ai-studio \|title=Cadence.AI: Transforming Chip Design with Agentic AI Workflows \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>		<ref name="CadenceAIOverview">{{cite web \|url=https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/transforming-chip-design-with-agentic-ai-introducing-cadence-cerebrus-ai-studio \|title=Cadence.AI: Transforming Chip Design with Agentic AI Workflows \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>
	<ref name="CadenceEDAWhatIs">{{cite web \|url=https://www.cadence.com/en_US/home/explore/what-is-electronic-design-automation.html#:~:text=Electronic%20design%20automation%20(EDA)%20is,hand%20and%20utilized%20siloed%20tools. \|title=What is Electronic Design Automation (EDA)? \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>		<ref name="CadenceEDAWhatIs">{{cite web \|url=https://www.cadence.com/en_US/home/explore/what-is-electronic-design-automation.html#:~:text=Electronic%20design%20automation%20(EDA)%20is,hand%20and%20utilized%20siloed%20tools. \|title=What is Electronic Design Automation (EDA)? \|publisher=Cadence Design Systems \|accessdate=June 7, 2025}}</ref>