Application-specific instruction set processor - Revision history

Dualpendel: Citations fixed

2025-05-10T12:49:09Z

Citations fixed

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	* {{cite book \|title=Embedded DSP Processor Design: Application Specific Instruction Set Processors \|author=Dake Liu \|year=2008 \|publisher=Elsevier Mogan Kaufmann \|location=MA \|isbn=978-0-12-374123-3 }}		* {{cite book \|title=Embedded DSP Processor Design: Application Specific Instruction Set Processors \|author=Dake Liu \|year=2008 \|publisher=Elsevier Mogan Kaufmann \|location=MA \|isbn=978-0-12-374123-3 }}
	* {{cite book \|title=Optimized ASIP Synthesis from Architecture Description Language Models \|author1=Oliver Schliebusch \|author2=Heinrich Meyr \|author3=Rainer Leupers \|year=2007 \|publisher=Springer \|location=Dordrecht \|isbn=978-1-4020-5685-7 }}		* {{cite book \|title=Optimized ASIP Synthesis from Architecture Description Language Models \|author1=Oliver Schliebusch \|author2=Heinrich Meyr \|author3=Rainer Leupers \|year=2007 \|publisher=Springer \|location=Dordrecht \|isbn=978-1-4020-5685-7 }}
	* {{cite book \|title=Customizable Embedded Processors ~~\|author=Paolo Ienne, Rainer Leupers (eds.)~~ \|year=2006 \|publisher=Morgan Kaufmann \|location=San Mateo, CA \|isbn=978-0-12-369526-0 }}		* {{cite book \|title=Customizable Embedded Processors \|year=2006 \|publisher=Morgan Kaufmann \|location=San Mateo, CA \|editor-last2=Ienne \|editor-first2=Paolo \|isbn=978-0-12-369526-0 \|editor-last=Leupers \|editor-first=Rainer}}
	* {{cite book \|title=Building ASIPs: The Mescal Methodology \|author=~~Matthias Gries, Kurt Keutzer (eds.)~~ \|year=2005 \|publisher=Springer \|location=New York \|isbn=978-0-387-26057-0 }}		* {{cite book \|title=Building ASIPs: The Mescal Methodology \|author= \|year=2005 \|publisher=Springer \|location=New York \|editor-last2=Keutzer \|editor-first2=Kurt \|isbn=978-0-387-26057-0 \|editor-last=Gries \|editor-first=Matthias}}

	==External links==		==External links==

MrOllie: rm advert

2023-08-09T12:44:16Z

rm advert

← Previous revision		Revision as of 12:44, 9 August 2023
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	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite book\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|title=VLSI Design 2001. Fourteenth International Conference on VLSI Design \|chapter=ASIP design methodologies: Survey and issues \|date=2001\|chapter-url=https://ieeexplore.ieee.org/document/902643\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite book\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|title=VLSI Design 2001. Fourteenth International Conference on VLSI Design \|chapter=ASIP design methodologies: Survey and issues \|date=2001\|chapter-url=https://ieeexplore.ieee.org/document/902643\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>

	ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).		ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref>

	== Examples ==		== Examples ==
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	==External links==		==External links==
	*[https://www.synopsys.com/dw/ipdir.php?ds=asip-designer ASIP Designer, proprietary tool suite from Synopsys enabling compiler-in-the-loop incremental design of ASIPs]
	*[https://codasip.com/codasip-studio/ Codasip Studio, proprietary tool suite from Codasip enabling design of ASIPs using CodAL processor description language]
	*[http://tce.cs.tut.fi TTA-Based Codesign Environment (TCE), an open source (MIT licensed) toolset for design of application specific TTA processors.]		*[http://tce.cs.tut.fi TTA-Based Codesign Environment (TCE), an open source (MIT licensed) toolset for design of application specific TTA processors.]

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2023-07-21T23:52:21Z

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← Previous revision		Revision as of 23:52, 21 July 2023
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	An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system on a chip]] design. The [[instruction set architecture]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit]] (CPU) and the performance of an [[application-specific integrated circuit]] (ASIC).		An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system on a chip]] design. The [[instruction set architecture]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit]] (CPU) and the performance of an [[application-specific integrated circuit]] (ASIC).

	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite ~~journal~~\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|~~date~~=2001\|~~title~~=ASIP design methodologies: ~~survey~~ and issues\|url=https://ieeexplore.ieee.org/document/902643~~\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design~~\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite book\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|title=VLSI Design 2001. Fourteenth International Conference on VLSI Design \|chapter=ASIP design methodologies: Survey and issues \|date=2001\|chapter-url=https://ieeexplore.ieee.org/document/902643\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>

	ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).		ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).

Ira Leviton: Fixed a typo.

2023-07-18T00:09:03Z

Fixed a typo.

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	== Examples ==		== Examples ==
	[[RISC-V\|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions.<ref>{{Cite book \|last=Krste \|first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi \|url=http://worldcat.org/oclc/913589579 \|title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 \|date=2014-05-06 \|oclc=913589579}}</ref> The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer ~~multiplcation~~/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.		[[RISC-V\|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions.<ref>{{Cite book \|last=Krste \|first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi \|url=http://worldcat.org/oclc/913589579 \|title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 \|date=2014-05-06 \|oclc=913589579}}</ref> The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplication/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.

	==See also==		==See also==

Jerryobject: WP:LINKs: updates, fix-cut needless WP:PIPEs (WP:NOPIPEs). MOS:FIRSTABBReviations clarify, define before WP:ABBRs in parentheses.

2022-12-11T17:49:53Z

WP:LINKs: updates, fix-cut needless WP:PIPEs (WP:NOPIPEs). MOS:FIRSTABBReviations clarify, define before WP:ABBRs in parentheses.

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	{{Short description\|Processor with an instruction set customized (optimized) for a specific task}}		{{Short description\|Processor with an instruction set customized (optimized) for a specific task}}
	{{Use American English\|date = March 2019}}		{{Use American English\|date=March 2019}}
	{{Use mdy dates\|date = March 2019}}		{{Use mdy dates\|date = March 2019}}
	{{More footnotes\|date=January 2015}}		{{More footnotes\|date=January 2015}}
	An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit~~\|CPU~~]] and the performance of an [[application-specific integrated circuit~~\|ASIC~~]].		An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system on a chip]] design. The [[instruction set architecture]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit]] (CPU) and the performance of an [[application-specific integrated circuit]] (ASIC).

	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=https://ieeexplore.ieee.org/document/902643\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=https://ieeexplore.ieee.org/document/902643\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>

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← Previous revision		Revision as of 11:09, 23 November 2022
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	An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].		An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].

	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|~~last~~=Jain\|~~first~~=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=~~http~~://ieeexplore.ieee.org/document/902643/\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3}}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=https://ieeexplore.ieee.org/document/902643\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>

	ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).		ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).

BattyBot: Fixed CS1 maint: extra punctuation and general fixes, removed stub tag

2022-10-08T02:56:00Z

Fixed CS1 maint: extra punctuation and general fixes, removed stub tag

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⚫	{{Use American English\|date = March 2019}}
	{{Short description\|Processor with an instruction set customized (optimized) for a specific task}}		{{Short description\|Processor with an instruction set customized (optimized) for a specific task}}
		⚫	{{Use American English\|date = March 2019}}
	{{Use mdy dates\|date = March 2019}}		{{Use mdy dates\|date = March 2019}}
	{{~~Inline~~ ~~citations~~\|date=January 2015}}		{{More footnotes\|date=January 2015}}
	An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].		An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].

	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last=Jain\|first=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=http://ieeexplore.ieee.org/document/902643/\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3}}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last=Jain\|first=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=http://ieeexplore.ieee.org/document/902643/\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3}}</ref>

	ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).		ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).

	== Examples ==		== Examples ==
	[[RISC-V\|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions<ref>{{Cite book \|last=Krste \|first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi, \|url=http://worldcat.org/oclc/913589579 \|title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 \|date=2014-05-06 \|oclc=913589579}}</ref>. The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplcation/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.		[[RISC-V\|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions.<ref>{{Cite book \|last=Krste \|first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi \|url=http://worldcat.org/oclc/913589579 \|title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 \|date=2014-05-06 \|oclc=913589579}}</ref> The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplcation/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.

	==See also==		==See also==
Line 38:		Line 38:
	[[Category:Instruction processing]]		[[Category:Instruction processing]]
	[[Category:Integrated circuits]]		[[Category:Integrated circuits]]

	{{Computer-hardware-stub}}

Aliyenimol: Added concrete examples for application-specific instructin set processors, e.g. modular design of RISC-V ISA.

2022-10-05T09:02:58Z

Added concrete examples for application-specific instructin set processors, e.g. modular design of RISC-V ISA.

← Previous revision		Revision as of 09:02, 5 October 2022
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	ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).		ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).

			== Examples ==
			[[RISC-V\|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions<ref>{{Cite book \|last=Krste \|first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi, \|url=http://worldcat.org/oclc/913589579 \|title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 \|date=2014-05-06 \|oclc=913589579}}</ref>. The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplcation/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.

	==See also==		==See also==

Hunan201p at 23:07, 10 September 2022

2022-09-10T23:07:57Z

← Previous revision		Revision as of 23:07, 10 September 2022
Line 5:		Line 5:
	An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].		An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].

	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last=Jain\|first=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=http://ieeexplore.ieee.org/document/902643/\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3}}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last=Jain\|first=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=http://ieeexplore.ieee.org/document/902643/\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3}}</ref>

	ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).		ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).

Kelvinkirunyu: /* top */ Spelling/grammar/punctuation/typographical correction

2022-04-13T20:21:30Z

top: Spelling/grammar/punctuation/typographical correction

← Previous revision		Revision as of 20:21, 13 April 2022
Line 5:		Line 5:
	An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].		An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit\|CPU]] and the performance of an [[application-specific integrated circuit\|ASIC]].

	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable ~~complier~~ generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last=Jain\|first=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=http://ieeexplore.ieee.org/document/902643/\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3}}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last=Jain\|first=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=http://ieeexplore.ieee.org/document/902643/\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3}}</ref>

	ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).		ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).

← Previous revision		Revision as of 12:49, 10 May 2025
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	* {{cite book \|title=Embedded DSP Processor Design: Application Specific Instruction Set Processors \|author=Dake Liu \|year=2008 \|publisher=Elsevier Mogan Kaufmann \|location=MA \|isbn=978-0-12-374123-3 }}		* {{cite book \|title=Embedded DSP Processor Design: Application Specific Instruction Set Processors \|author=Dake Liu \|year=2008 \|publisher=Elsevier Mogan Kaufmann \|location=MA \|isbn=978-0-12-374123-3 }}
	* {{cite book \|title=Optimized ASIP Synthesis from Architecture Description Language Models \|author1=Oliver Schliebusch \|author2=Heinrich Meyr \|author3=Rainer Leupers \|year=2007 \|publisher=Springer \|location=Dordrecht \|isbn=978-1-4020-5685-7 }}		* {{cite book \|title=Optimized ASIP Synthesis from Architecture Description Language Models \|author1=Oliver Schliebusch \|author2=Heinrich Meyr \|author3=Rainer Leupers \|year=2007 \|publisher=Springer \|location=Dordrecht \|isbn=978-1-4020-5685-7 }}
	* {{cite book \|title=Customizable Embedded Processors ~~\|author=Paolo Ienne, Rainer Leupers (eds.)~~ \|year=2006 \|publisher=Morgan Kaufmann \|location=San Mateo, CA \|isbn=978-0-12-369526-0 }}		* {{cite book \|title=Customizable Embedded Processors \|year=2006 \|publisher=Morgan Kaufmann \|location=San Mateo, CA \|editor-last2=Ienne \|editor-first2=Paolo \|isbn=978-0-12-369526-0 \|editor-last=Leupers \|editor-first=Rainer}}
	* {{cite book \|title=Building ASIPs: The Mescal Methodology \|author=~~Matthias Gries, Kurt Keutzer (eds.)~~ \|year=2005 \|publisher=Springer \|location=New York \|isbn=978-0-387-26057-0 }}		* {{cite book \|title=Building ASIPs: The Mescal Methodology \|author= \|year=2005 \|publisher=Springer \|location=New York \|editor-last2=Keutzer \|editor-first2=Kurt \|isbn=978-0-387-26057-0 \|editor-last=Gries \|editor-first=Matthias}}

	==External links==		==External links==

← Previous revision		Revision as of 17:49, 11 December 2022
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	{{Short description\|Processor with an instruction set customized (optimized) for a specific task}}		{{Short description\|Processor with an instruction set customized (optimized) for a specific task}}
	{{Use American English\|date = March 2019}}		{{Use American English\|date=March 2019}}
	{{Use mdy dates\|date = March 2019}}		{{Use mdy dates\|date = March 2019}}
	{{More footnotes\|date=January 2015}}		{{More footnotes\|date=January 2015}}
	An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit~~\|CPU~~]] and the performance of an [[application-specific integrated circuit~~\|ASIC~~]].		An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system on a chip]] design. The [[instruction set architecture]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit]] (CPU) and the performance of an [[application-specific integrated circuit]] (ASIC).

	Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=https://ieeexplore.ieee.org/document/902643\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>		Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal\|last1=Jain\|first1=M.K.\|last2=Balakrishnan\|first2=M.\|last3=Kumar\|first3=A.\|date=2001\|title=ASIP design methodologies: survey and issues\|url=https://ieeexplore.ieee.org/document/902643\|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design\|location=Bangalore, India\|publisher=IEEE Comput. Soc\|pages=76–81\|doi=10.1109/ICVD.2001.902643\|isbn=978-0-7695-0831-3\|s2cid=14053636 }}</ref>