Direct memory access - Revision history

160.227.20.254: Add a link

2025-05-29T17:12:31Z

Add a link

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	=== Bus mastering ===		=== Bus mastering ===
	In a [[bus mastering]] system, also known as a first-party DMA system, the CPU and peripherals can each be granted control of the memory bus. Where a peripheral can become a bus master, it can directly write to system memory without the involvement of the CPU, providing memory address and control signals as required. Some measures must be provided to put the processor into a hold condition so that bus contention does not occur.		In a [[bus mastering]] system, also known as a first-party DMA system, the CPU and peripherals can each be granted control of the memory bus. Where a peripheral can become a bus master, it can directly write to system memory without the involvement of the CPU, providing memory address and control signals as required. Some measures must be provided to put the processor into a hold condition so that [[bus contention]] does not occur.

	== Modes of operation==		== Modes of operation==

OAbot: Open access bot: url-access updated in citation with #oabot.

2025-05-24T23:01:09Z

Open access bot: url-access updated in citation with #oabot.

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	As an example usage of DMA in a [[multiprocessor-system-on-chip]], IBM/Sony/Toshiba's [[Cell processor]] incorporates a DMA engine for each of its 9 processing elements including one Power processor element (PPE) and eight synergistic processor elements (SPEs). Since the SPE's load/store instructions can read/write only its own local memory, an SPE entirely depends on DMAs to transfer data to and from the main memory and local memories of other SPEs. Thus the DMA acts as a primary means of data transfer among cores inside this [[CPU]] (in contrast to cache-coherent CMP architectures such as Intel's cancelled [[GPGPU\|general-purpose GPU]], [[Larrabee (microarchitecture)\|Larrabee]]).		As an example usage of DMA in a [[multiprocessor-system-on-chip]], IBM/Sony/Toshiba's [[Cell processor]] incorporates a DMA engine for each of its 9 processing elements including one Power processor element (PPE) and eight synergistic processor elements (SPEs). Since the SPE's load/store instructions can read/write only its own local memory, an SPE entirely depends on DMAs to transfer data to and from the main memory and local memories of other SPEs. Thus the DMA acts as a primary means of data transfer among cores inside this [[CPU]] (in contrast to cache-coherent CMP architectures such as Intel's cancelled [[GPGPU\|general-purpose GPU]], [[Larrabee (microarchitecture)\|Larrabee]]).

	DMA in Cell is fully [[#Cache coherency\|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache\|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite journal \|first=Michael \|last=Kistler \|title=Cell Multiprocessor Communication Network: Built for Speed \|journal=[[IEEE Micro]] \|date=May 2006\|volume=26 \|issue=3 \|pages=10–23 \|doi=10.1109/MM.2006.49 \|s2cid=7735690 \|url=http://portal.acm.org/citation.cfm?id=1158825.1159067 }}</ref>		DMA in Cell is fully [[#Cache coherency\|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache\|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite journal \|first=Michael \|last=Kistler \|title=Cell Multiprocessor Communication Network: Built for Speed \|journal=[[IEEE Micro]] \|date=May 2006\|volume=26 \|issue=3 \|pages=10–23 \|doi=10.1109/MM.2006.49 \|s2cid=7735690 \|url=http://portal.acm.org/citation.cfm?id=1158825.1159067 \|url-access=subscription }}</ref>

	== DMA controllers ==		== DMA controllers ==

45.148.12.42: Dead link for first reference, updated link to a healthy link to the same paper.

2025-04-26T12:20:26Z

Dead link for first reference, updated link to a healthy link to the same paper.

← Previous revision		Revision as of 12:20, 26 April 2025
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	With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA's extended 24-bit address bus width allows it to access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.		With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA's extended 24-bit address bus width allows it to access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.

	Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://~~www~~.~~ing.unlp~~.edu~~.ar~~/~~catedras~~/~~E0225~~/~~descargar~~.~~php?secc=0&id=E0225&id_inc=1196~~ \|~~website~~=~~Universidad~~ ~~Nacional~~ ~~de la Plata, Argentina~~ \|~~access-date~~=20 ~~April~~ ~~2019~~}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.		Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://cires1.colorado.edu/jimenez-group/QAMSResources/Docs/DMAFundamentals.pdf \|access-date=26 April 2025 \|website=University of Colorado Boulder}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.

	Each DMA channel has a 16-bit address register and a 16-bit count register associated with it. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to begin the transfer. When the transfer is complete, the device [[interrupt]]s the CPU.		Each DMA channel has a 16-bit address register and a 16-bit count register associated with it. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to begin the transfer. When the transfer is complete, the device [[interrupt]]s the CPU.

Kvng: improve language

2025-04-25T13:08:49Z

improve language

← Previous revision		Revision as of 13:08, 25 April 2025
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	In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.		In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.

	With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA extended bus width ~~to 24-bit, make~~ it ~~can~~ access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.		With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA's extended 24-bit address bus width allows it to access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.

	Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.		Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.

Randomdude121: Reverted edits by 103.83.29.248 (talk) (AV)

2025-04-20T14:44:23Z

Reverted edits by 103.83.29.248 (talk) (AV)

← Previous revision		Revision as of 14:44, 20 April 2025
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	'''Direct memory access''' ('''DMA''') is a feature of computer systems that allows certain hardware subsystems to access main system [[computer memory\|memory]] independently of the [[central processing unit]] (CPU).<ref name="DMAfundamentals" />		'''Direct memory access''' ('''DMA''') is a feature of computer systems that allows certain hardware subsystems to access main system [[computer memory\|memory]] independently of the [[central processing unit]] (CPU).<ref name="DMAfundamentals" />
	hi

	Without DMA, when the CPU is using [[programmed input/output]], it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an [[interrupt]] from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer.		Without DMA, when the CPU is using [[programmed input/output]], it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an [[interrupt]] from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer.

103.83.29.248 at 14:44, 20 April 2025

2025-04-20T14:44:02Z

← Previous revision		Revision as of 14:44, 20 April 2025
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	'''Direct memory access''' ('''DMA''') is a feature of computer systems that allows certain hardware subsystems to access main system [[computer memory\|memory]] independently of the [[central processing unit]] (CPU).<ref name="DMAfundamentals" />		'''Direct memory access''' ('''DMA''') is a feature of computer systems that allows certain hardware subsystems to access main system [[computer memory\|memory]] independently of the [[central processing unit]] (CPU).<ref name="DMAfundamentals" />
			hi

	Without DMA, when the CPU is using [[programmed input/output]], it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an [[interrupt]] from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer.		Without DMA, when the CPU is using [[programmed input/output]], it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an [[interrupt]] from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer.

43.230.11.9 at 08:46, 20 April 2025

2025-04-20T08:46:46Z

← Previous revision		Revision as of 08:46, 20 April 2025
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	In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.		In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.

	With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.		With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA extended bus width to 24-bit, make it can access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.

	Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.		Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.

Kvng: Reverted 1 edit by 103.163.44.85 (talk) to last revision by Maury Markowitz

2025-02-24T14:42:38Z

Reverted 1 edit by 103.163.44.85 (talk) to last revision by Maury Markowitz

← Previous revision		Revision as of 14:42, 24 February 2025
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	DMA in Cell is fully [[#Cache coherency\|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache\|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite journal \|first=Michael \|last=Kistler \|title=Cell Multiprocessor Communication Network: Built for Speed \|journal=[[IEEE Micro]] \|date=May 2006\|volume=26 \|issue=3 \|pages=10–23 \|doi=10.1109/MM.2006.49 \|s2cid=7735690 \|url=http://portal.acm.org/citation.cfm?id=1158825.1159067 }}</ref>		DMA in Cell is fully [[#Cache coherency\|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache\|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite journal \|first=Michael \|last=Kistler \|title=Cell Multiprocessor Communication Network: Built for Speed \|journal=[[IEEE Micro]] \|date=May 2006\|volume=26 \|issue=3 \|pages=10–23 \|doi=10.1109/MM.2006.49 \|s2cid=7735690 \|url=http://portal.acm.org/citation.cfm?id=1158825.1159067 }}</ref>

	== DMA controllers: ==		== DMA controllers ==
	* [[Intel 8257]]		* [[Intel 8257]]
	* Am9517<ref>{{Cite web \|url=http://www.bitsavers.org/components/amd/_dataSheets/Am9517A.pdf \|title=Am9517A Multimode DMA Controller \|accessdate=2024-01-06}}</ref>		* Am9517<ref>{{Cite web \|url=http://www.bitsavers.org/components/amd/_dataSheets/Am9517A.pdf \|title=Am9517A Multimode DMA Controller \|accessdate=2024-01-06}}</ref>
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	* μPD71037,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=832 \|title=pPD71037 Direct Memory Access (DMA) Controller \|page=832(5b1) \|accessdate=2024-01-06}}</ref> capable of addressing a 64K-byte of memory		* μPD71037,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=832 \|title=pPD71037 Direct Memory Access (DMA) Controller \|page=832(5b1) \|accessdate=2024-01-06}}</ref> capable of addressing a 64K-byte of memory
	* μPD71071,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=940 \|title=µPD71071 DMA Controller \|page=940(5g1)\|accessdate=2024-01-05}}</ref> capable of addressing a 16M-byte of memory		* μPD71071,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=940 \|title=µPD71071 DMA Controller \|page=940(5g1)\|accessdate=2024-01-05}}</ref> capable of addressing a 16M-byte of memory


	== Pipelining ==		== Pipelining ==

103.163.44.85: /* DMA controllers: */

2025-02-20T11:55:40Z

DMA controllers:

← Previous revision		Revision as of 11:55, 20 February 2025
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	DMA in Cell is fully [[#Cache coherency\|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache\|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite journal \|first=Michael \|last=Kistler \|title=Cell Multiprocessor Communication Network: Built for Speed \|journal=[[IEEE Micro]] \|date=May 2006\|volume=26 \|issue=3 \|pages=10–23 \|doi=10.1109/MM.2006.49 \|s2cid=7735690 \|url=http://portal.acm.org/citation.cfm?id=1158825.1159067 }}</ref>		DMA in Cell is fully [[#Cache coherency\|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache\|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite journal \|first=Michael \|last=Kistler \|title=Cell Multiprocessor Communication Network: Built for Speed \|journal=[[IEEE Micro]] \|date=May 2006\|volume=26 \|issue=3 \|pages=10–23 \|doi=10.1109/MM.2006.49 \|s2cid=7735690 \|url=http://portal.acm.org/citation.cfm?id=1158825.1159067 }}</ref>

	== DMA controllers ==		== DMA controllers: ==
	* [[Intel 8257]]		* [[Intel 8257]]
	* Am9517<ref>{{Cite web \|url=http://www.bitsavers.org/components/amd/_dataSheets/Am9517A.pdf \|title=Am9517A Multimode DMA Controller \|accessdate=2024-01-06}}</ref>		* Am9517<ref>{{Cite web \|url=http://www.bitsavers.org/components/amd/_dataSheets/Am9517A.pdf \|title=Am9517A Multimode DMA Controller \|accessdate=2024-01-06}}</ref>
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	* μPD71037,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=832 \|title=pPD71037 Direct Memory Access (DMA) Controller \|page=832(5b1) \|accessdate=2024-01-06}}</ref> capable of addressing a 64K-byte of memory		* μPD71037,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=832 \|title=pPD71037 Direct Memory Access (DMA) Controller \|page=832(5b1) \|accessdate=2024-01-06}}</ref> capable of addressing a 64K-byte of memory
	* μPD71071,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=940 \|title=µPD71071 DMA Controller \|page=940(5g1)\|accessdate=2024-01-05}}</ref> capable of addressing a 16M-byte of memory		* μPD71071,<ref>{{Cite web \|url=http://bitsavers.informatik.uni-stuttgart.de/components/nec/_dataBooks/1990_NEC_16-bit_V-Series_Microprocessor_Data_Book.pdf#page=940 \|title=µPD71071 DMA Controller \|page=940(5g1)\|accessdate=2024-01-05}}</ref> capable of addressing a 16M-byte of memory


	== Pipelining ==		== Pipelining ==

Maury Markowitz at 13:18, 20 December 2024

2024-12-20T13:18:59Z

← Previous revision		Revision as of 13:18, 20 December 2024
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	'''Direct memory access''' ('''DMA''') is a feature of computer systems that allows certain hardware subsystems to access main system [[computer memory\|memory]] independently of the [[central processing unit]] (CPU).<ref name="DMAfundamentals" />		'''Direct memory access''' ('''DMA''') is a feature of computer systems that allows certain hardware subsystems to access main system [[computer memory\|memory]] independently of the [[central processing unit]] (CPU).<ref name="DMAfundamentals" />

	Without DMA, when the CPU is using [[programmed input/output]], it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an [[interrupt]] from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including [[disk drive]] controllers, [[graphics card]]s, [[network card]]s and [[sound card]]s. DMA is also used for intra-chip data transfer in some [[multi-core processor]]s. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels. Similarly, a [[processing element\|processing circuitry]] inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.		Without DMA, when the CPU is using [[programmed input/output]], it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an [[interrupt]] from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer.

			Many hardware systems use DMA, including [[disk drive]] controllers, [[graphics card]]s, [[network card]]s and [[sound card]]s. DMA is also used for intra-chip data transfer in some [[multi-core processor]]s. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels. Similarly, a [[processing element\|processing circuitry]] inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.

	DMA can also be used for "memory to memory" copying or moving of data within memory. DMA can offload expensive memory operations, such as large copies or [[scatter-gather]] operations, from the CPU to a dedicated DMA engine. An implementation example is the [[I/O Acceleration Technology]]. DMA is of interest in [[network-on-chip]] and [[in-memory computing]] architectures.		DMA can also be used for "memory to memory" copying or moving of data within memory. DMA can offload expensive memory operations, such as large copies or [[scatter-gather]] operations, from the CPU to a dedicated DMA engine. An implementation example is the [[I/O Acceleration Technology]]. DMA is of interest in [[network-on-chip]] and [[in-memory computing]] architectures.

← Previous revision		Revision as of 13:08, 25 April 2025
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	In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.		In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.

	With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA extended bus width ~~to 24-bit, make~~ it ~~can~~ access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.		With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA's extended 24-bit address bus width allows it to access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.

	Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.		Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.

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	In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.		In the original [[IBM PC]] (and the follow-up [[PC/XT]]), there was only one [[Intel 8237]] DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's [[i8088]] CPU/bus architecture), could only address the first ([[i8086]]/8088-standard) megabyte of RAM, and were limited to addressing single 64 [[kilobyte\|kB]] segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1, of which channel 0 in the PC (& XT) was dedicated to [[dynamic memory]] [[memory refresh\|refresh]]. This prevented it from being used as a general-purpose "[[Blitter]]", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.

	With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.		With the [[IBM PC/AT]], the enhanced [[AT bus]] (more familiarly retronymed as the [[Industry Standard Architecture]] (ISA)) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). ISA DMA extended bus width to 24-bit, make it can access up to 16 MB lower memory.<ref>{{Cite web \|title=ISA DMA - OSDev Wiki \|url=https://wiki.osdev.org/ISA_DMA \|access-date=2025-04-20 \|website=wiki.osdev.org}}</ref> The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply ''controlling'' the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised [[80286]] running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB [[x86 memory segmentation\|segment boundary]] issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to monopolise the bus approximately every 15 [[μs]] prevented use of large (and fast, but uninterruptible) block transfers.

	Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.		Due to their lagging performance (1.6 [[megabyte\|MB]]/s maximum 8-bit transfer capability at 5 MHz,<ref name="i8237sheet">{{cite web \|title=Intel 8237 & 8237-2 Datasheet \|url=http://www.jbox.dk/rc702/hardware/intel-8237.pdf \|website=JKbox RC702 subsite \|access-date=20 April 2019}}</ref> but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions<ref name="DMAfundamentals">{{cite web \|title=DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7 \|url=https://www.ing.unlp.edu.ar/catedras/E0225/descargar.php?secc=0&id=E0225&id_inc=1196 \|website=Universidad Nacional de la Plata, Argentina \|access-date=20 April 2019}}</ref>) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the [[80386]] processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the [[80186]] meant that PIO transfers even by the 16-bit-bus [[80286\|286]] and [[80386SX\|386SX]] could still easily outstrip the 8237), as well as the development of further evolutions to ([[Extended Industry Standard Architecture\|EISA]]) or replacements for ([[Micro Channel architecture\|MCA]], [[VESA local bus\|VLB]] and [[Peripheral Component Interconnect\|PCI]]) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were [[Sound Blaster]] cards that needed to maintain full hardware compatibility with the [[Sound Blaster standard]]; and [[Super I/O]] devices on motherboards that often integrated a built-in [[floppy disk]] controller, an [[IrDA]] infrared controller when FIR (fast infrared) mode is selected, and an [[IEEE 1284]] parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main [[RAM]] regardless of the system's actual address space or amount of installed memory.