Explicitly parallel instruction computing - Revision history

88.241.81.167: "No instruction set computing" and "One-instruction set computer" added to See also.

2024-11-06T17:44:01Z

"No instruction set computing" and "One-instruction set computer" added to See also.

← Previous revision		Revision as of 17:44, 6 November 2024
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	*[[Minimal instruction set computer]] (MISC)		*[[Minimal instruction set computer]] (MISC)
	*[[Very long instruction word]] (VLIW)		*[[Very long instruction word]] (VLIW)
			*[[No instruction set computing]]
			*[[One-instruction set computer]]
	*[[Computer architecture]]		*[[Computer architecture]]
	*[[Superscalar_processor\|Superscalar]]		*[[Superscalar_processor\|Superscalar]]

Whoop whoop pull up: /* Roots in VLIW */

2024-03-23T19:39:45Z

Roots in VLIW

← Previous revision		Revision as of 19:39, 23 March 2024
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	''VLIW'' (at least the original forms) has several short-comings that precluded it from becoming mainstream:		''VLIW'' (at least the original forms) has several short-comings that precluded it from becoming mainstream:
	* VLIW [[instruction set]]s are not [[backward compatibility\|backward compatible]] between implementations. When [[wide-issue\|wider]] implementations (more [[execution unit]]s) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.		* VLIW [[instruction set]]s are not [[backward compatibility\|backward compatible]] between implementations. When [[wide-issue\|wider]] implementations (more [[execution unit]]s) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
	* Load responses from a [[memory hierarchy]] which includes [[CPU cache]]s and [[DRAM]] do not have a deterministic delay. This makes static scheduling of load instructions by the compiler very difficult.		* Load responses from a [[memory hierarchy]] which includes [[CPU cache]]s and [[DRAM]] do not have a deterministic delay.{{why\|date=March 2024}} This makes static scheduling of load instructions by the compiler very difficult.
	EPIC architecture evolved from VLIW architecture, but retained many concepts of the [[superscalar]] architecture.		EPIC architecture evolved from VLIW architecture, but retained many concepts of the [[superscalar]] architecture.

Whoop whoop pull up: /* Roots in VLIW */ Fixing link.

2024-03-23T19:39:12Z

Roots in VLIW: Fixing link.

← Previous revision		Revision as of 19:39, 23 March 2024
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	By 1989, researchers at HP recognized that [[reduced instruction set computer]] (RISC) architectures were reaching a limit at one [[instruction per cycle]].{{Clarify\|date=September 2009}} They began an investigation into a new architecture, later named '''EPIC'''.<ref name="HP_Labs"/> The basis for the research was [[Very long instruction word\|VLIW]], in which multiple operations are encoded in every instruction, and then processed by multiple execution units.		By 1989, researchers at HP recognized that [[reduced instruction set computer]] (RISC) architectures were reaching a limit at one [[instruction per cycle]].{{Clarify\|date=September 2009}} They began an investigation into a new architecture, later named '''EPIC'''.<ref name="HP_Labs"/> The basis for the research was [[Very long instruction word\|VLIW]], in which multiple operations are encoded in every instruction, and then processed by multiple execution units.

	One goal of EPIC was to move the complexity of instruction scheduling from the CPU hardware to the software [[compiler]], which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal was to further exploit [[instruction level parallelism]] (''ILP'') by using the compiler to find and exploit additional opportunities for [[parallel computing\|parallel execution]].		One goal of EPIC was to move the complexity of instruction scheduling from the CPU hardware to the software [[compiler]], which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal was to further exploit [[instruction-level parallelism]] (''ILP'') by using the compiler to find and exploit additional opportunities for [[parallel computing\|parallel execution]].

	''VLIW'' (at least the original forms) has several short-comings that precluded it from becoming mainstream:		''VLIW'' (at least the original forms) has several short-comings that precluded it from becoming mainstream:

InternetArchiveBot: Rescuing 1 sources and tagging 0 as dead.) #IABot (v2.0.9.5

2024-03-23T19:19:47Z

Rescuing 1 sources and tagging 0 as dead.) #IABot (v2.0.9.5

← Previous revision		Revision as of 19:19, 23 March 2024
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	\| title = Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture		\| title = Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture
	\| access-date = 2007-12-14		\| access-date = 2007-12-14
	\|date=June 2001		\| date = June 2001
	\| work = [[Hewlett-Packard\|HP]] Labs		\| work = [[Hewlett-Packard\|HP]] Labs
			\| archive-date = 2012-03-04
			\| archive-url = https://web.archive.org/web/20120304045612/http://www.hpl.hp.com/news/2001/apr-jun/itanium.html
			\| url-status = dead
	}}</ref> and [[Hewlett-Packard\|HP]] later asserted that "EPIC" was merely an old term for the Itanium architecture.<ref name="anand">{{cite web		}}</ref> and [[Hewlett-Packard\|HP]] later asserted that "EPIC" was merely an old term for the Itanium architecture.<ref name="anand">{{cite web
	\| url = http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598		\| url = http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598

Arch dude: Undid revision 1160478078 by 24.175.241.187 (talk) good faith but unreferenced addition.

2023-06-16T18:59:02Z

Undid revision 1160478078 by 24.175.241.187 (talk) good faith but unreferenced addition.

← Previous revision		Revision as of 18:59, 16 June 2023
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	{{Refimprove\|date=October 2010}}		{{Refimprove\|date=October 2010}}

	'''Explicitly ~~Parallel~~ ~~Instruction~~ ~~Computing~~''' ('''EPIC''')~~, sometimes called '''Explicit Parallelism In Code''',~~ is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web		'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web
	\|url = http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf		\|url = http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf
	\|format=PDF\|title = EPIC: An Architecture for Instruction-Level Parallel Processors		\|format=PDF\|title = EPIC: An Architecture for Instruction-Level Parallel Processors

24.175.241.187: Explicit Parallelism In Code alternative acronym

2023-06-16T18:46:38Z

Explicit Parallelism In Code alternative acronym

← Previous revision		Revision as of 18:46, 16 June 2023
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	{{Refimprove\|date=October 2010}}		{{Refimprove\|date=October 2010}}

	'''Explicitly ~~parallel~~ ~~instruction~~ ~~computing~~''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web		'''Explicitly Parallel Instruction Computing''' ('''EPIC'''), sometimes called '''Explicit Parallelism In Code''', is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web
	\|url = http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf		\|url = http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf
	\|format=PDF\|title = EPIC: An Architecture for Instruction-Level Parallel Processors		\|format=PDF\|title = EPIC: An Architecture for Instruction-Level Parallel Processors

86.172.174.29: /* See also */

2023-02-15T01:53:47Z

YourLocalZenith: /* top */

2022-11-24T10:28:25Z

top

← Previous revision		Revision as of 10:28, 24 November 2022
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	{{short description\|Instruction set architecture}}		{{short description\|Instruction set architecture}}
	{{Refimprove\|date=October 2010}}		{{Refimprove\|date=October 2010}}
	{{distinguish\|text= [[Epyc]]}}

	'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web		'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web

YourLocalZenith at 08:18, 17 September 2022

2022-09-17T08:18:30Z

← Previous revision		Revision as of 08:18, 17 September 2022
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	{{short description\|Instruction set architecture}}		{{short description\|Instruction set architecture}}
	{{Refimprove\|date=October 2010}}		{{Refimprove\|date=October 2010}}
			{{distinguish\|text= [[Epyc]]}}

	'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web		'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web

Skullcinema: cite patent fix

2022-05-05T15:29:42Z

cite patent fix

← Previous revision		Revision as of 15:29, 5 May 2022
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	\|work = HP Laboratories Palo Alto, HPL-1999-111		\|work = HP Laboratories Palo Alto, HPL-1999-111
	\|date=February 2000		\|date=February 2000
	}}</ref> to describe a [[computing paradigm]] that researchers had been investigating since the early 1980s.<ref>{{cite patent\|US\|4847755}}</ref> This paradigm is also called ''Independence'' architectures. It was the basis for [[Intel]] and [[Hewlett-Packard\|HP]] development of the Intel [[Itanium]] architecture,<ref name="HP_Labs">{{cite web		}}</ref> to describe a [[computing paradigm]] that researchers had been investigating since the early 1980s.<ref>{{cite patent\|country=US\|number=4847755\|pubdate=1989-07-11\|title=Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies\|assign1=MCC Development Ltd.\|inventor1-last=Morrison\|inventor1-first=Gordon E.\|inventor2-last=Brooks\|inventor2-first=Christopher B.\|inventor3-last=Gluck\|inventor3-first=Frederick G.}}</ref> This paradigm is also called ''Independence'' architectures. It was the basis for [[Intel]] and [[Hewlett-Packard\|HP]] development of the Intel [[Itanium]] architecture,<ref name="HP_Labs">{{cite web
	\| url = http://www.hpl.hp.com/news/2001/apr-jun/itanium.html		\| url = http://www.hpl.hp.com/news/2001/apr-jun/itanium.html
	\| title = Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture		\| title = Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture

← Previous revision		Revision as of 01:53, 15 February 2023
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	*[[Complex instruction set computer]] (CISC)		*[[Complex instruction set computer]] (CISC)
	*[[Reduced instruction set computer]] (RISC)		*[[Reduced instruction set computer]] (RISC)
			*[[Minimal instruction set computer]] (MISC)
	*[[Very long instruction word]] (VLIW)		*[[Very long instruction word]] (VLIW)
	*[[Computer architecture]]		*[[Computer architecture]]

← Previous revision		Revision as of 10:28, 24 November 2022
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	{{short description\|Instruction set architecture}}		{{short description\|Instruction set architecture}}
	{{Refimprove\|date=October 2010}}		{{Refimprove\|date=October 2010}}
	{{distinguish\|text= [[Epyc]]}}

	'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web		'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web

← Previous revision		Revision as of 08:18, 17 September 2022
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	{{short description\|Instruction set architecture}}		{{short description\|Instruction set architecture}}
	{{Refimprove\|date=October 2010}}		{{Refimprove\|date=October 2010}}
			{{distinguish\|text= [[Epyc]]}}

	'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web		'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium\|HP–Intel alliance]]<ref>{{cite web