Field-programmable gate array - Revision history

Ralf Moses: /* See also */

2025-06-17T16:18:10Z

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2025-06-16T02:13:01Z

lc common nouns

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	=== Integration ===		=== Integration ===
	In 2012 the coarse-grained architectural approach was taken a step further by combining the [[logic block]]s and interconnects of traditional FPGAs with embedded [[microprocessor]]s and related peripherals to form a complete [[System on a chip\|system on a programmable chip]]. Examples of such hybrid technologies can be found in the [[Xilinx]] Zynq-7000 all [[~~Programmable~~ SoC]],<ref name="Xilinx-Inc-Oct-2011-8-K">{{cite web\|url=http://edgar.secdatabase.com/520/95012311090713/filing-main.htm \|title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 19, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> which includes a 1.0 [[GHz]] dual-core [[ARM Cortex-A9]] MPCore processor [[Embedded system\|embedded]] within the FPGA's logic fabric,<ref name="Xilinx-Inc-May-2011-10-K">{{cite web\|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm \|title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> or in the [[Altera]] Arria V FPGA, which includes an 800 MHz [[dual-core]] [[ARM Cortex-A9]] MPCore. The [[Atmel]] FPSLIC is another such device, which uses an [[Atmel AVR\|AVR]] processor in combination with Atmel's programmable logic architecture. The [[Microsemi]] [[SmartFusion]] devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of [[Flash memory\|flash]] and 64 kB of RAM) and analog [[peripheral]]s such as a multi-channel [[analog-to-digital converter]]s and [[digital-to-analog converter]]s in their [[flash memory]]-based FPGA fabric.{{cn\|date=November 2022}}		In 2012 the coarse-grained architectural approach was taken a step further by combining the [[logic block]]s and interconnects of traditional FPGAs with embedded [[microprocessor]]s and related peripherals to form a complete [[System on a chip\|system on a programmable chip]]. Examples of such hybrid technologies can be found in the [[Xilinx]] Zynq-7000 all [[programmable SoC]],<ref name="Xilinx-Inc-Oct-2011-8-K">{{cite web\|url=http://edgar.secdatabase.com/520/95012311090713/filing-main.htm \|title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 19, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> which includes a 1.0 [[GHz]] dual-core [[ARM Cortex-A9]] MPCore processor [[Embedded system\|embedded]] within the FPGA's logic fabric,<ref name="Xilinx-Inc-May-2011-10-K">{{cite web\|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm \|title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> or in the [[Altera]] Arria V FPGA, which includes an 800 MHz [[dual-core]] [[ARM Cortex-A9]] MPCore. The [[Atmel]] FPSLIC is another such device, which uses an [[Atmel AVR\|AVR]] processor in combination with Atmel's programmable logic architecture. The [[Microsemi]] [[SmartFusion]] devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of [[Flash memory\|flash]] and 64 kB of RAM) and analog [[peripheral]]s such as a multi-channel [[analog-to-digital converter]]s and [[digital-to-analog converter]]s in their [[flash memory]]-based FPGA fabric.{{cn\|date=November 2022}}

	=== Clocking ===		=== Clocking ===
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	* [[Achronix]], manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<ref>{{Cite press release \|url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|title=Achronix to Use Intel's 22nm Manufacturing \|date=2010-11-01 \|work=Intel Newsroom \|access-date=2018-12-01 \|language=en-US \|archive-date=2015-09-30 \|archive-url=https://web.archive.org/web/20150930082224/http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|url-status=dead }}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>		* [[Achronix]], manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<ref>{{Cite press release \|url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|title=Achronix to Use Intel's 22nm Manufacturing \|date=2010-11-01 \|work=Intel Newsroom \|access-date=2018-12-01 \|language=en-US \|archive-date=2015-09-30 \|archive-url=https://web.archive.org/web/20150930082224/http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|url-status=dead }}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>
	*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book \|last1=Maxfield \|first1=Clive \|title=The Design Warrior's Guide to FPGAs \|date=16 June 2004 \|publisher=Elsevier Science \|isbn=9780080477138 \|url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>		*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book \|last1=Maxfield \|first1=Clive \|title=The Design Warrior's Guide to FPGAs \|date=16 June 2004 \|publisher=Elsevier Science \|isbn=9780080477138 \|url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>
	* Cologne Chip, German ~~Government~~ backed designer and producer of FPGAs<ref>{{Cite web \|title=About the company – Cologne Chip \|url=https://colognechip.com/about-the-company/ \|access-date=2024-02-27 \|language=en-US}}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>		* Cologne Chip, German government-backed designer and producer of FPGAs<ref>{{Cite web \|title=About the company – Cologne Chip \|url=https://colognechip.com/about-the-company/ \|access-date=2024-02-27 \|language=en-US}}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>
	* [[Efinix]] offers small to medium-sized FPGAs. They combine logic and routing interconnects into a configurable XLR cell.{{cn\|date=September 2024}}		* [[Efinix]] offers small to medium-sized FPGAs. They combine logic and routing interconnects into a configurable XLR cell.{{cn\|date=September 2024}}
	* [[GOWIN Semiconductors]], manufacturing small and medium-sized SRAM and ~~Flash~~-based FPGAs. They also offer pin-compatible replacements for a few Xilinx, Altera and Lattice products.{{cn\|date=September 2024}}		* [[GOWIN Semiconductors]], manufacturing small and medium-sized SRAM and flash-based FPGAs. They also offer pin-compatible replacements for a few Xilinx, Altera and Lattice products.{{cn\|date=September 2024}}
	* [[Lattice Semiconductor]] manufactures [[Low-power electronics\|low-power]] SRAM-based FPGAs featuring integrated configuration flash, [[instant-on]] and live [[Reconfigurable computing\|reconfiguration]]		* [[Lattice Semiconductor]] manufactures [[Low-power electronics\|low-power]] SRAM-based FPGAs featuring integrated configuration flash, [[instant-on]] and live [[Reconfigurable computing\|reconfiguration]]
	** [[SiliconBlue Technologies]] provides extremely low-power SRAM-based FPGAs with optional integrated [[Non-volatile memory\|nonvolatile]] configuration memory; acquired by Lattice in 2011		** [[SiliconBlue Technologies]] provides extremely low-power SRAM-based FPGAs with optional integrated [[Non-volatile memory\|nonvolatile]] configuration memory; acquired by Lattice in 2011
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	In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical [[Backdoor (computing)\|backdoor]] [[Vulnerability (computing)\|vulnerability]] had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and [[access key]]s, accessing unencrypted bitstream, modifying [[low-level]] silicon features, and extracting [[Computer configuration\|configuration]] data.<ref>{{cite book \|volume=7428\|pages=23–40\|doi=10.1007/978-3-642-33027-8_2\|series = Lecture Notes in Computer Science\|year = 2012\|last1 = Skorobogatov\|first1 = Sergei\|title=Cryptographic Hardware and Embedded Systems – CHES 2012\|last2=Woods\|first2=Christopher\|isbn=978-3-642-33026-1\|chapter=Breakthrough Silicon Scanning Discovers Backdoor in Military Chip}}</ref>		In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical [[Backdoor (computing)\|backdoor]] [[Vulnerability (computing)\|vulnerability]] had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and [[access key]]s, accessing unencrypted bitstream, modifying [[low-level]] silicon features, and extracting [[Computer configuration\|configuration]] data.<ref>{{cite book \|volume=7428\|pages=23–40\|doi=10.1007/978-3-642-33027-8_2\|series = Lecture Notes in Computer Science\|year = 2012\|last1 = Skorobogatov\|first1 = Sergei\|title=Cryptographic Hardware and Embedded Systems – CHES 2012\|last2=Woods\|first2=Christopher\|isbn=978-3-642-33026-1\|chapter=Breakthrough Silicon Scanning Discovers Backdoor in Military Chip}}</ref>

	In 2020 a critical vulnerability (named "Starbleed") was discovered in all Xilinx ~~7series~~ FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.		In 2020 a critical vulnerability (named "Starbleed") was discovered in all Xilinx 7 series FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.

	== Similar technologies ==		== Similar technologies ==

InternetArchiveBot: Rescuing 1 sources and tagging 0 as dead.) #IABot (v2.0.9.5

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Rescuing 1 sources and tagging 0 as dead.) #IABot (v2.0.9.5

← Previous revision		Revision as of 04:06, 5 June 2025
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	Other manufacturers include:		Other manufacturers include:

	* [[Achronix]], manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<ref>{{Cite press release \|url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|title=Achronix to Use Intel's 22nm Manufacturing\|date=2010-11-01 \|work=Intel Newsroom \|access-date=2018-12-01 \|language=en-US}}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>		* [[Achronix]], manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<ref>{{Cite press release \|url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|title=Achronix to Use Intel's 22nm Manufacturing \|date=2010-11-01 \|work=Intel Newsroom \|access-date=2018-12-01 \|language=en-US \|archive-date=2015-09-30 \|archive-url=https://web.archive.org/web/20150930082224/http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|url-status=dead }}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>
	*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book \|last1=Maxfield \|first1=Clive \|title=The Design Warrior's Guide to FPGAs \|date=16 June 2004 \|publisher=Elsevier Science \|isbn=9780080477138 \|url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>		*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book \|last1=Maxfield \|first1=Clive \|title=The Design Warrior's Guide to FPGAs \|date=16 June 2004 \|publisher=Elsevier Science \|isbn=9780080477138 \|url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>
	* Cologne Chip, German Government backed designer and producer of FPGAs<ref>{{Cite web \|title=About the company – Cologne Chip \|url=https://colognechip.com/about-the-company/ \|access-date=2024-02-27 \|language=en-US}}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>		* Cologne Chip, German Government backed designer and producer of FPGAs<ref>{{Cite web \|title=About the company – Cologne Chip \|url=https://colognechip.com/about-the-company/ \|access-date=2024-02-27 \|language=en-US}}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>

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Manufacturers: ce

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	== Manufacturers ==		== Manufacturers ==
	In 2016, long-time industry rivals [[Xilinx]] (now part of [[AMD]]) and [[Altera]] (now part of [[Intel~~\|İntel~~]]) were the FPGA market leaders.<ref>{{cite web \|first=Paul \|last=Dillien \|work=EETimes \| url=http://www.eetimes.com/author.asp?doc_id=1331443 \| archive-url =https://web.archive.org/web/20190105015123/http://www.eetimes.com/author.asp?doc_id=1331443 \|title=And the Winner of Best FPGA of 2016 is... \|date=March 6, 2017 \|access-date=September 7, 2017 \|archive-date=January 5, 2019 }}</ref> At that time, they controlled nearly 90 percent of the market.		In 2016, long-time industry rivals [[Xilinx]] (now part of [[AMD]]) and [[Altera]] (now part of [[Intel]]) were the FPGA market leaders.<ref>{{cite web \|first=Paul \|last=Dillien \|work=EETimes \| url=http://www.eetimes.com/author.asp?doc_id=1331443 \| archive-url =https://web.archive.org/web/20190105015123/http://www.eetimes.com/author.asp?doc_id=1331443 \|title=And the Winner of Best FPGA of 2016 is... \|date=March 6, 2017 \|access-date=September 7, 2017 \|archive-date=January 5, 2019 }}</ref> At that time, they controlled nearly 90 percent of the market.

	Both Xilinx (now AMD) and Altera (now Intel) provide [[proprietary software\|proprietary]] [[electronic design automation]] software for [[Windows]] and [[Linux]] ([[Xilinx ISE\|ISE]]/[[Vivado]] and [[Intel Quartus Prime\|Quartus]]) which enables engineers to [[Hardware design\|design]], analyze, [[simulate]], and [[Logic synthesis\|synthesize]] ([[compile]]) their designs.<ref>{{Cite web\|url=https://www.xilinx.com/products/design-tools/ise-design-suite.html\|title=Xilinx ISE Design Suite\|website=www.xilinx.com\|access-date=2018-12-01}}</ref><ref>{{Cite web\|url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/overview.html\|title=FPGA Design Software - Intel Quartus Prime\|website=Intel\|language=en\|access-date=2018-12-01}}</ref>		Both Xilinx (now AMD) and Altera (now Intel) provide [[proprietary software\|proprietary]] [[electronic design automation]] software for [[Windows]] and [[Linux]] ([[Xilinx ISE\|ISE]]/[[Vivado]] and [[Intel Quartus Prime\|Quartus]]) which enables engineers to [[Hardware design\|design]], analyze, [[simulate]], and [[Logic synthesis\|synthesize]] ([[compile]]) their designs.<ref>{{Cite web\|url=https://www.xilinx.com/products/design-tools/ise-design-suite.html\|title=Xilinx ISE Design Suite\|website=www.xilinx.com\|access-date=2018-12-01}}</ref><ref>{{Cite web\|url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/overview.html\|title=FPGA Design Software - Intel Quartus Prime\|website=Intel\|language=en\|access-date=2018-12-01}}</ref>

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	=== Usage by United States military ===		=== Usage by United States military ===
	FPGAs play a crucial role in modern military communications, especially in systems like the [[Joint Tactical Radio System]] (JTRS) and in devices from companies such as [[Thales Group\|Thales]] and [[Harris Corporation]]. Their flexibility and programmability make them ideal for military communications, offering customizable and secure signal processing. In the JTRS, used by the US military, FPGAs provide adaptability and real-time processing, crucial for meeting various communication standards and encryption methods.<ref>{{Cite web \|date=2004-12-01 \|title=Software-defined radio and JTRS \|url=https://www.militaryaerospace.com/computers/article/16710419/softwaredefined-radio-and-jtrs \|access-date=2024-01-17 \|website=Military Aerospace}}</ref~~><!--[[User:Kvng/RTH]]--~~>		FPGAs play a crucial role in modern military communications, especially in systems like the [[Joint Tactical Radio System]] (JTRS) and in devices from companies such as [[Thales Group\|Thales]] and [[Harris Corporation]]. Their flexibility and programmability make them ideal for military communications, offering customizable and secure signal processing. In the JTRS, used by the US military, FPGAs provide adaptability and real-time processing, crucial for meeting various communication standards and encryption methods.<ref>{{Cite web \|date=2004-12-01 \|title=Software-defined radio and JTRS \|url=https://www.militaryaerospace.com/computers/article/16710419/softwaredefined-radio-and-jtrs \|access-date=2024-01-17 \|website=Military Aerospace}}</ref>

	== Security ==		== Security ==
		⚫	Concerning [[hardware security]], FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors. FPGAs' flexibility makes malicious modifications during [[Semiconductor device fabrication\|fabrication]] a lower risk.<ref name="paper">{{Cite journal \|doi=10.1109/MDT.2008.166 \|title=Managing Security in FPGA-Based Embedded Systems \|journal=IEEE Design & Test of Computers \|volume=25 \|issue=6 \|pages=590–598 \|year=2008 \|last1=Huffmire \|first1=Ted \|last2=Brotherton \|first2=Brett \|last3=Sherwood \|first3=Timothy \|last4=Kastner \|first4=Ryan \|last5=Levin \|first5=Timothy \|last6=Nguyen \|first6=Thuy D. \|last7=Irvine \|first7=Cynthia\|s2cid=115840 \|hdl=10945/7159 \|hdl-access=free }}</ref> Previously, for many FPGAs, the design [[bitstream]] was exposed while the FPGA loads it from external memory, typically during powerup. All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream [[encryption]] and [[authentication]]. For example, [[Altera]] and [[Xilinx]] offer [[Advanced Encryption Standard\|AES]] encryption (up to 256-bit) for bitstreams stored in an external flash memory. [[Physical unclonable function]]s (PUFs) are integrated circuits that have their own unique signatures and can be used to secure FPGAs while taking up very little hardware space.<ref>{{Cite journal \|last1=Babaei \|first1=Armin \|last2=Schiele \|first2=Gregor \|last3=Zohner \|first3=Michael \|date=2022-07-26 \|title=Reconfigurable Security Architecture (RESA) Based on PUF for FPGA-Based IoT Devices \|journal=Sensors \|language=en \|volume=22 \|issue=15 \|pages=5577 \|doi=10.3390/s22155577 \|issn=1424-8220 \|pmc=9331300 \|pmid=35898079 \|bibcode=2022Senso..22.5577B \|doi-access=free }}</ref><!--[[User:Kvng/RTH]]-->

⚫	FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors~~, concerning [[hardware security]]~~. FPGAs' flexibility makes malicious modifications during [[Semiconductor device fabrication\|fabrication]] a lower risk.<ref name="paper">{{Cite journal \|doi=10.1109/MDT.2008.166 \|title=Managing Security in FPGA-Based Embedded Systems \|journal=IEEE Design & Test of Computers \|volume=25 \|issue=6 \|pages=590–598 \|year=2008 \|last1=Huffmire \|first1=Ted \|last2=Brotherton \|first2=Brett \|last3=Sherwood \|first3=Timothy \|last4=Kastner \|first4=Ryan \|last5=Levin \|first5=Timothy \|last6=Nguyen \|first6=Thuy D. \|last7=Irvine \|first7=Cynthia\|s2cid=115840 \|hdl=10945/7159 \|hdl-access=free }}</ref> Previously, for many FPGAs, the design [[bitstream]] was exposed while the FPGA loads it from external memory (typically on ~~every power-on)~~. All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream [[encryption]] and [[authentication]]. For example, [[Altera]] and [[Xilinx]] offer [[Advanced Encryption Standard\|AES]] encryption (up to 256-bit) for bitstreams stored in an external flash memory. [[Physical unclonable function]]s (PUFs) are integrated circuits that have their own unique signatures~~, due to processing,~~ and can ~~also~~ be used to secure FPGAs while taking up very little hardware space.<ref>{{Cite journal \|last1=Babaei \|first1=Armin \|last2=Schiele \|first2=Gregor \|last3=Zohner \|first3=Michael \|date=2022-07-26 \|title=Reconfigurable Security Architecture (RESA) Based on PUF for FPGA-Based IoT Devices \|journal=Sensors \|language=en \|volume=22 \|issue=15 \|pages=5577 \|doi=10.3390/s22155577 \|issn=1424-8220 \|pmc=9331300 \|pmid=35898079 \|bibcode=2022Senso..22.5577B \|doi-access=free }}</ref>

	FPGAs that store their configuration internally in nonvolatile flash memory, such as [[Microsemi]]'s ProAsic 3 or [[Lattice Semiconductor\|Lattice]]'s XP2 programmable devices, do not expose the bitstream and do not need [[encryption]]. In addition, flash memory for a [[lookup table]] provides [[single event upset]] protection for space applications.{{clarify\|date=January 2013}} Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as [[Microsemi]].		FPGAs that store their configuration internally in nonvolatile flash memory, such as [[Microsemi]]'s ProAsic 3 or [[Lattice Semiconductor\|Lattice]]'s XP2 programmable devices, do not expose the bitstream and do not need [[encryption]]. In addition, flash memory for a [[lookup table]] provides [[single event upset]] protection for space applications.{{clarify\|date=January 2013}} Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as [[Microsemi]].

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	* Space (with [[radiation hardening]]<ref>{{Cite web\|url=https://www.militaryaerospace.com/articles/2016/06/radiation-hardened-space-fpga.html\|title=FPGA development devices for radiation-hardened space applications introduced by Microsemi\|website=www.militaryaerospace.com\|access-date=2018-11-02\|date=2016-06-03}}</ref>)		* Space (with [[radiation hardening]]<ref>{{Cite web\|url=https://www.militaryaerospace.com/articles/2016/06/radiation-hardened-space-fpga.html\|title=FPGA development devices for radiation-hardened space applications introduced by Microsemi\|website=www.militaryaerospace.com\|access-date=2018-11-02\|date=2016-06-03}}</ref>)
	* [[Hardware security module]]s<ref name="auto">{{cite web\|title=CrypTech: Building Transparency into Cryptography t \|url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-date=2016-08-07 \|url-status=live}}</ref>		* [[Hardware security module]]s<ref name="auto">{{cite web\|title=CrypTech: Building Transparency into Cryptography t \|url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-date=2016-08-07 \|url-status=live}}</ref>
	* High-speed financial transactions<ref>{{Cite web \|last=Mann \|first=Tobias \|date=2023-03-08 \|title=While Intel XPUs are delayed, here's some more FPGAs to tide you over \|url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ \|website=The Register}}</ref><ref>{{Cite conference \|url=https://ieeexplore.ieee.org/document/6044837 \|title=High Frequency Trading Acceleration Using FPGAs \|last1=Leber \|first1=Christian \|last2=Geib \|first2=Benjamin \|last3=Litz \|first3=Heiner \|doi=10.1109/FPL.2011.64 \|publisher=IEEE \|date=September 2011 \|conference=International Conference on Field Programmable Logic and Applications}}</ref>		* High-speed financial transactions<ref>{{Cite web \|last=Mann \|first=Tobias \|date=2023-03-08 \|title=While Intel XPUs are delayed, here's some more FPGAs to tide you over \|url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ \|website=The Register}}</ref><ref>{{Cite conference \|url=https://ieeexplore.ieee.org/document/6044837 \|title=High Frequency Trading Acceleration Using FPGAs \|last1=Leber \|first1=Christian \|last2=Geib \|first2=Benjamin \|last3=Litz \|first3=Heiner \|doi=10.1109/FPL.2011.64 \|publisher=IEEE \|date=September 2011 \|conference=International Conference on Field Programmable Logic and Applications\|url-access=subscription }}</ref>
	* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{cite web \|url=https://www.retrorgb.com/the-diy-mister-handheld.html \|title=The DIY MiSTer Handheld \|date=16 December 2024 \|access-date=}}</ref>		* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{cite web \|url=https://www.retrorgb.com/the-diy-mister-handheld.html \|title=The DIY MiSTer Handheld \|date=16 December 2024 \|access-date=}}</ref>
	* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>		* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>

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 === Usage by United States military ===
 FPGAs play a crucial role in modern military communications, especially in systems like the [[Joint Tactical Radio System]] (JTRS) and in devices from companies such as [[Thales Group|Thales]] and [[Harris Corporation]]. Their flexibility and programmability make them ideal for military communications, offering customizable and secure signal processing. In the JTRS, used by the US military, FPGAs provide adaptability and real-time processing, crucial for meeting various communication standards and encryption methods.<ref>{{Cite web |date=2004-12-01 |title=Software-defined radio and JTRS |url=https://www.militaryaerospace.com/computers/article/16710419/softwaredefined-radio-and-jtrs |access-date=2024-01-17 |website=Military Aerospace}}</ref><!--[[User:Kvng/RTH]]-->
 == Security ==

Citation bot: Added date. | Use this bot. Report bugs. | Suggested by Dominic3203 | Linked from User:LinguisticMystic/cs/outline | #UCB_webform_linked 733/2277

2025-04-16T20:06:17Z

Added date. | Use this bot. Report bugs. | Suggested by Dominic3203 | Linked from User:LinguisticMystic/cs/outline | #UCB_webform_linked 733/2277

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	* [[Hardware security module]]s<ref name="auto">{{cite web\|title=CrypTech: Building Transparency into Cryptography t \|url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-date=2016-08-07 \|url-status=live}}</ref>		* [[Hardware security module]]s<ref name="auto">{{cite web\|title=CrypTech: Building Transparency into Cryptography t \|url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-date=2016-08-07 \|url-status=live}}</ref>
	* High-speed financial transactions<ref>{{Cite web \|last=Mann \|first=Tobias \|date=2023-03-08 \|title=While Intel XPUs are delayed, here's some more FPGAs to tide you over \|url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ \|website=The Register}}</ref><ref>{{Cite conference \|url=https://ieeexplore.ieee.org/document/6044837 \|title=High Frequency Trading Acceleration Using FPGAs \|last1=Leber \|first1=Christian \|last2=Geib \|first2=Benjamin \|last3=Litz \|first3=Heiner \|doi=10.1109/FPL.2011.64 \|publisher=IEEE \|date=September 2011 \|conference=International Conference on Field Programmable Logic and Applications}}</ref>		* High-speed financial transactions<ref>{{Cite web \|last=Mann \|first=Tobias \|date=2023-03-08 \|title=While Intel XPUs are delayed, here's some more FPGAs to tide you over \|url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ \|website=The Register}}</ref><ref>{{Cite conference \|url=https://ieeexplore.ieee.org/document/6044837 \|title=High Frequency Trading Acceleration Using FPGAs \|last1=Leber \|first1=Christian \|last2=Geib \|first2=Benjamin \|last3=Litz \|first3=Heiner \|doi=10.1109/FPL.2011.64 \|publisher=IEEE \|date=September 2011 \|conference=International Conference on Field Programmable Logic and Applications}}</ref>
	* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{cite web \|url=https://www.retrorgb.com/the-diy-mister-handheld.html \|title=The DIY MiSTer Handheld \|access-date=}}</ref>		* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{cite web \|url=https://www.retrorgb.com/the-diy-mister-handheld.html \|title=The DIY MiSTer Handheld \|date=16 December 2024 \|access-date=}}</ref>
	* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>		* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>

Leyo: format

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format

← Previous revision		Revision as of 21:45, 13 April 2025
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	* {{cite book\|title=Digital Circuit Design An Introduction Textbook \|first=Niklaus \|last=Wirth \|publisher=Springer \|year=1995 \|isbn=978-3-540-58577-0}}		* {{cite book\|title=Digital Circuit Design An Introduction Textbook \|first=Niklaus \|last=Wirth \|publisher=Springer \|year=1995 \|isbn=978-3-540-58577-0}}
	* {{cite journal\|title=An FPGA-Based Phase Measurement System \|journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems \|volume=26 \|pages=133–142 \|first=Jubin \|last=Mitra \|publisher=IEEE \|year=2018 \|doi=10.1109/TVLSI.2017.2758807\|s2cid=4920719 \|doi-access=free }}		* {{cite journal\|title=An FPGA-Based Phase Measurement System \|journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems \|volume=26 \|pages=133–142 \|first=Jubin \|last=Mitra \|publisher=IEEE \|year=2018 \|doi=10.1109/TVLSI.2017.2758807\|s2cid=4920719 \|doi-access=free }}
	* Mencer, Oskar et al. (2020). "The history, status, and future of FPGAs". Communications of the ACM. ACM. Vol. 63, No. 10. ~~doi:~~[[doi:~~10.1145/3410669\|~~10.1145/3410669]]		* Mencer, Oskar et al. (2020). "The history, status, and future of FPGAs". Communications of the ACM. ACM. Vol. 63, No. 10. [[doi:10.1145/3410669]]

	== External links ==		== External links ==

InternetArchiveBot: Rescuing 0 sources and tagging 1 as dead.) #IABot (v2.0.9.5

2025-04-07T11:05:27Z

Rescuing 0 sources and tagging 1 as dead.) #IABot (v2.0.9.5

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	The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<ref>{{Cite journal \|last1=Alcaín \|first1=Eduardo \|last2=Fernández \|first2=Pedro R. \|last3=Nieto \|first3=Rubén \|last4=Montemayor \|first4=Antonio S. \|last5=Vilas \|first5=Jaime \|last6=Galiana-Bordera \|first6=Adrian \|last7=Martinez-Girones \|first7=Pedro Miguel \|last8=Prieto-de-la-Lastra \|first8=Carmen \|last9=Rodriguez-Vila \|first9=Borja \|last10=Bonet \|first10=Marina \|last11=Rodriguez-Sanchez \|first11=Cristina \|date=2021-12-15 \|title=Hardware Architectures for Real-Time Medical Imaging \|journal=Electronics \|language=en \|volume=10 \|issue=24 \|pages=3118 \|doi=10.3390/electronics10243118 \|issn=2079-9292\|doi-access=free }}</ref><ref>{{Cite journal \|last1=Nagornov \|first1=Nikolay N. \|last2=Lyakhov \|first2=Pavel A. \|last3=Valueva \|first3=Maria V. \|last4=Bergerman \|first4=Maxim V. \|date=2022 \|title=RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients \|journal=IEEE Access \|volume=10 \|pages=19215–19231 \|doi=10.1109/ACCESS.2022.3151361 \|s2cid=246895876 \|issn=2169-3536\|doi-access=free \|bibcode=2022IEEEA..1019215N }}</ref> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.		The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<ref>{{Cite journal \|last1=Alcaín \|first1=Eduardo \|last2=Fernández \|first2=Pedro R. \|last3=Nieto \|first3=Rubén \|last4=Montemayor \|first4=Antonio S. \|last5=Vilas \|first5=Jaime \|last6=Galiana-Bordera \|first6=Adrian \|last7=Martinez-Girones \|first7=Pedro Miguel \|last8=Prieto-de-la-Lastra \|first8=Carmen \|last9=Rodriguez-Vila \|first9=Borja \|last10=Bonet \|first10=Marina \|last11=Rodriguez-Sanchez \|first11=Cristina \|date=2021-12-15 \|title=Hardware Architectures for Real-Time Medical Imaging \|journal=Electronics \|language=en \|volume=10 \|issue=24 \|pages=3118 \|doi=10.3390/electronics10243118 \|issn=2079-9292\|doi-access=free }}</ref><ref>{{Cite journal \|last1=Nagornov \|first1=Nikolay N. \|last2=Lyakhov \|first2=Pavel A. \|last3=Valueva \|first3=Maria V. \|last4=Bergerman \|first4=Maxim V. \|date=2022 \|title=RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients \|journal=IEEE Access \|volume=10 \|pages=19215–19231 \|doi=10.1109/ACCESS.2022.3151361 \|s2cid=246895876 \|issn=2169-3536\|doi-access=free \|bibcode=2022IEEEA..1019215N }}</ref> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.

	Another trend in the use of FPGAs is [[hardware acceleration]], where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engine [[Bing (search engine)\|Bing]] is noted for adopting FPGA acceleration for its search algorithm in 2014.<ref name="BingFPGA">{{cite news \|last1=Morgan \|first1=Timothy Pricket \|title=How Microsoft Is Using FPGAs To Speed Up Bing Search \|url=https://www.enterprisetech.com/2014/09/03/microsoft-using-fpgas-speed-bing-search/ \|access-date=2018-09-18 \|publisher=Enterprise Tech \|date=2014-09-03}}</ref> {{as of\|2018}}, FPGAs are seeing increased use as [[AI accelerator]]s including Microsoft's Project Catapult<ref name="ProjCatapult">{{cite web\|url=https://www.microsoft.com/en-us/research/project/project-catapult/\|title=Project Catapult\|date=July 2018\|website=Microsoft Research}}</ref> and for accelerating [[artificial neural network]]s for [[machine learning]] applications.		Another trend in the use of FPGAs is [[hardware acceleration]], where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engine [[Bing (search engine)\|Bing]] is noted for adopting FPGA acceleration for its search algorithm in 2014.<ref name="BingFPGA">{{cite news \|last1=Morgan \|first1=Timothy Pricket \|title=How Microsoft Is Using FPGAs To Speed Up Bing Search \|url=https://www.enterprisetech.com/2014/09/03/microsoft-using-fpgas-speed-bing-search/ \|access-date=2018-09-18 \|publisher=Enterprise Tech \|date=2014-09-03 }}{{Dead link\|date=April 2025 \|bot=InternetArchiveBot \|fix-attempted=yes }}</ref> {{as of\|2018}}, FPGAs are seeing increased use as [[AI accelerator]]s including Microsoft's Project Catapult<ref name="ProjCatapult">{{cite web\|url=https://www.microsoft.com/en-us/research/project/project-catapult/\|title=Project Catapult\|date=July 2018\|website=Microsoft Research}}</ref> and for accelerating [[artificial neural network]]s for [[machine learning]] applications.

	Originally,{{When\|date=October 2018}} FPGAs were reserved for specific [[vertical application]]s where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.{{cn\|date=December 2024}}		Originally,{{When\|date=October 2018}} FPGAs were reserved for specific [[vertical application]]s where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.{{cn\|date=December 2024}}

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	{{Portal\|Electronics}}		{{Portal\|Electronics}}
	* [[FPGA Mezzanine Card]]		* [[FPGA Mezzanine Card]]
	* [[CRUVI FPGA Card~~\|CRUVI~~ FPGA ~~daughtercard~~ standard]]		* [[CRUVI FPGA Card]] FPGA daughter card standard of Standardization Group for Embedded Technologies e.V. (SGET)
	* [[List of HDL simulators]]		* [[List of HDL simulators]]

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	=== Integration ===		=== Integration ===
	In 2012 the coarse-grained architectural approach was taken a step further by combining the [[logic block]]s and interconnects of traditional FPGAs with embedded [[microprocessor]]s and related peripherals to form a complete [[System on a chip\|system on a programmable chip]]. Examples of such hybrid technologies can be found in the [[Xilinx]] Zynq-7000 all [[~~Programmable~~ SoC]],<ref name="Xilinx-Inc-Oct-2011-8-K">{{cite web\|url=http://edgar.secdatabase.com/520/95012311090713/filing-main.htm \|title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 19, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> which includes a 1.0 [[GHz]] dual-core [[ARM Cortex-A9]] MPCore processor [[Embedded system\|embedded]] within the FPGA's logic fabric,<ref name="Xilinx-Inc-May-2011-10-K">{{cite web\|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm \|title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> or in the [[Altera]] Arria V FPGA, which includes an 800 MHz [[dual-core]] [[ARM Cortex-A9]] MPCore. The [[Atmel]] FPSLIC is another such device, which uses an [[Atmel AVR\|AVR]] processor in combination with Atmel's programmable logic architecture. The [[Microsemi]] [[SmartFusion]] devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of [[Flash memory\|flash]] and 64 kB of RAM) and analog [[peripheral]]s such as a multi-channel [[analog-to-digital converter]]s and [[digital-to-analog converter]]s in their [[flash memory]]-based FPGA fabric.{{cn\|date=November 2022}}		In 2012 the coarse-grained architectural approach was taken a step further by combining the [[logic block]]s and interconnects of traditional FPGAs with embedded [[microprocessor]]s and related peripherals to form a complete [[System on a chip\|system on a programmable chip]]. Examples of such hybrid technologies can be found in the [[Xilinx]] Zynq-7000 all [[programmable SoC]],<ref name="Xilinx-Inc-Oct-2011-8-K">{{cite web\|url=http://edgar.secdatabase.com/520/95012311090713/filing-main.htm \|title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 19, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> which includes a 1.0 [[GHz]] dual-core [[ARM Cortex-A9]] MPCore processor [[Embedded system\|embedded]] within the FPGA's logic fabric,<ref name="Xilinx-Inc-May-2011-10-K">{{cite web\|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm \|title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 \|publisher=secdatabase.com \|access-date =May 6, 2018}}</ref> or in the [[Altera]] Arria V FPGA, which includes an 800 MHz [[dual-core]] [[ARM Cortex-A9]] MPCore. The [[Atmel]] FPSLIC is another such device, which uses an [[Atmel AVR\|AVR]] processor in combination with Atmel's programmable logic architecture. The [[Microsemi]] [[SmartFusion]] devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of [[Flash memory\|flash]] and 64 kB of RAM) and analog [[peripheral]]s such as a multi-channel [[analog-to-digital converter]]s and [[digital-to-analog converter]]s in their [[flash memory]]-based FPGA fabric.{{cn\|date=November 2022}}

	=== Clocking ===		=== Clocking ===
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	* [[Achronix]], manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<ref>{{Cite press release \|url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|title=Achronix to Use Intel's 22nm Manufacturing \|date=2010-11-01 \|work=Intel Newsroom \|access-date=2018-12-01 \|language=en-US \|archive-date=2015-09-30 \|archive-url=https://web.archive.org/web/20150930082224/http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|url-status=dead }}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>		* [[Achronix]], manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<ref>{{Cite press release \|url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|title=Achronix to Use Intel's 22nm Manufacturing \|date=2010-11-01 \|work=Intel Newsroom \|access-date=2018-12-01 \|language=en-US \|archive-date=2015-09-30 \|archive-url=https://web.archive.org/web/20150930082224/http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing \|url-status=dead }}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>
	*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book \|last1=Maxfield \|first1=Clive \|title=The Design Warrior's Guide to FPGAs \|date=16 June 2004 \|publisher=Elsevier Science \|isbn=9780080477138 \|url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>		*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book \|last1=Maxfield \|first1=Clive \|title=The Design Warrior's Guide to FPGAs \|date=16 June 2004 \|publisher=Elsevier Science \|isbn=9780080477138 \|url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>
	* Cologne Chip, German ~~Government~~ backed designer and producer of FPGAs<ref>{{Cite web \|title=About the company – Cologne Chip \|url=https://colognechip.com/about-the-company/ \|access-date=2024-02-27 \|language=en-US}}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>		* Cologne Chip, German government-backed designer and producer of FPGAs<ref>{{Cite web \|title=About the company – Cologne Chip \|url=https://colognechip.com/about-the-company/ \|access-date=2024-02-27 \|language=en-US}}{{better source needed\|{{subst:DATE}}\|date=September 2024}}</ref>
	* [[Efinix]] offers small to medium-sized FPGAs. They combine logic and routing interconnects into a configurable XLR cell.{{cn\|date=September 2024}}		* [[Efinix]] offers small to medium-sized FPGAs. They combine logic and routing interconnects into a configurable XLR cell.{{cn\|date=September 2024}}
	* [[GOWIN Semiconductors]], manufacturing small and medium-sized SRAM and ~~Flash~~-based FPGAs. They also offer pin-compatible replacements for a few Xilinx, Altera and Lattice products.{{cn\|date=September 2024}}		* [[GOWIN Semiconductors]], manufacturing small and medium-sized SRAM and flash-based FPGAs. They also offer pin-compatible replacements for a few Xilinx, Altera and Lattice products.{{cn\|date=September 2024}}
	* [[Lattice Semiconductor]] manufactures [[Low-power electronics\|low-power]] SRAM-based FPGAs featuring integrated configuration flash, [[instant-on]] and live [[Reconfigurable computing\|reconfiguration]]		* [[Lattice Semiconductor]] manufactures [[Low-power electronics\|low-power]] SRAM-based FPGAs featuring integrated configuration flash, [[instant-on]] and live [[Reconfigurable computing\|reconfiguration]]
	** [[SiliconBlue Technologies]] provides extremely low-power SRAM-based FPGAs with optional integrated [[Non-volatile memory\|nonvolatile]] configuration memory; acquired by Lattice in 2011		** [[SiliconBlue Technologies]] provides extremely low-power SRAM-based FPGAs with optional integrated [[Non-volatile memory\|nonvolatile]] configuration memory; acquired by Lattice in 2011
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	In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical [[Backdoor (computing)\|backdoor]] [[Vulnerability (computing)\|vulnerability]] had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and [[access key]]s, accessing unencrypted bitstream, modifying [[low-level]] silicon features, and extracting [[Computer configuration\|configuration]] data.<ref>{{cite book \|volume=7428\|pages=23–40\|doi=10.1007/978-3-642-33027-8_2\|series = Lecture Notes in Computer Science\|year = 2012\|last1 = Skorobogatov\|first1 = Sergei\|title=Cryptographic Hardware and Embedded Systems – CHES 2012\|last2=Woods\|first2=Christopher\|isbn=978-3-642-33026-1\|chapter=Breakthrough Silicon Scanning Discovers Backdoor in Military Chip}}</ref>		In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical [[Backdoor (computing)\|backdoor]] [[Vulnerability (computing)\|vulnerability]] had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and [[access key]]s, accessing unencrypted bitstream, modifying [[low-level]] silicon features, and extracting [[Computer configuration\|configuration]] data.<ref>{{cite book \|volume=7428\|pages=23–40\|doi=10.1007/978-3-642-33027-8_2\|series = Lecture Notes in Computer Science\|year = 2012\|last1 = Skorobogatov\|first1 = Sergei\|title=Cryptographic Hardware and Embedded Systems – CHES 2012\|last2=Woods\|first2=Christopher\|isbn=978-3-642-33026-1\|chapter=Breakthrough Silicon Scanning Discovers Backdoor in Military Chip}}</ref>

	In 2020 a critical vulnerability (named "Starbleed") was discovered in all Xilinx ~~7series~~ FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.		In 2020 a critical vulnerability (named "Starbleed") was discovered in all Xilinx 7 series FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.

	== Similar technologies ==		== Similar technologies ==

← Previous revision		Revision as of 11:46, 24 May 2025
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	* Space (with [[radiation hardening]]<ref>{{Cite web\|url=https://www.militaryaerospace.com/articles/2016/06/radiation-hardened-space-fpga.html\|title=FPGA development devices for radiation-hardened space applications introduced by Microsemi\|website=www.militaryaerospace.com\|access-date=2018-11-02\|date=2016-06-03}}</ref>)		* Space (with [[radiation hardening]]<ref>{{Cite web\|url=https://www.militaryaerospace.com/articles/2016/06/radiation-hardened-space-fpga.html\|title=FPGA development devices for radiation-hardened space applications introduced by Microsemi\|website=www.militaryaerospace.com\|access-date=2018-11-02\|date=2016-06-03}}</ref>)
	* [[Hardware security module]]s<ref name="auto">{{cite web\|title=CrypTech: Building Transparency into Cryptography t \|url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-date=2016-08-07 \|url-status=live}}</ref>		* [[Hardware security module]]s<ref name="auto">{{cite web\|title=CrypTech: Building Transparency into Cryptography t \|url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf \|archive-date=2016-08-07 \|url-status=live}}</ref>
	* High-speed financial transactions<ref>{{Cite web \|last=Mann \|first=Tobias \|date=2023-03-08 \|title=While Intel XPUs are delayed, here's some more FPGAs to tide you over \|url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ \|website=The Register}}</ref><ref>{{Cite conference \|url=https://ieeexplore.ieee.org/document/6044837 \|title=High Frequency Trading Acceleration Using FPGAs \|last1=Leber \|first1=Christian \|last2=Geib \|first2=Benjamin \|last3=Litz \|first3=Heiner \|doi=10.1109/FPL.2011.64 \|publisher=IEEE \|date=September 2011 \|conference=International Conference on Field Programmable Logic and Applications}}</ref>		* High-speed financial transactions<ref>{{Cite web \|last=Mann \|first=Tobias \|date=2023-03-08 \|title=While Intel XPUs are delayed, here's some more FPGAs to tide you over \|url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ \|website=The Register}}</ref><ref>{{Cite conference \|url=https://ieeexplore.ieee.org/document/6044837 \|title=High Frequency Trading Acceleration Using FPGAs \|last1=Leber \|first1=Christian \|last2=Geib \|first2=Benjamin \|last3=Litz \|first3=Heiner \|doi=10.1109/FPL.2011.64 \|publisher=IEEE \|date=September 2011 \|conference=International Conference on Field Programmable Logic and Applications\|url-access=subscription }}</ref>
	* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{cite web \|url=https://www.retrorgb.com/the-diy-mister-handheld.html \|title=The DIY MiSTer Handheld \|date=16 December 2024 \|access-date=}}</ref>		* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{cite web \|url=https://www.retrorgb.com/the-diy-mister-handheld.html \|title=The DIY MiSTer Handheld \|date=16 December 2024 \|access-date=}}</ref>
	* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>		* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>

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	The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<ref>{{Cite journal \|last1=Alcaín \|first1=Eduardo \|last2=Fernández \|first2=Pedro R. \|last3=Nieto \|first3=Rubén \|last4=Montemayor \|first4=Antonio S. \|last5=Vilas \|first5=Jaime \|last6=Galiana-Bordera \|first6=Adrian \|last7=Martinez-Girones \|first7=Pedro Miguel \|last8=Prieto-de-la-Lastra \|first8=Carmen \|last9=Rodriguez-Vila \|first9=Borja \|last10=Bonet \|first10=Marina \|last11=Rodriguez-Sanchez \|first11=Cristina \|date=2021-12-15 \|title=Hardware Architectures for Real-Time Medical Imaging \|journal=Electronics \|language=en \|volume=10 \|issue=24 \|pages=3118 \|doi=10.3390/electronics10243118 \|issn=2079-9292\|doi-access=free }}</ref><ref>{{Cite journal \|last1=Nagornov \|first1=Nikolay N. \|last2=Lyakhov \|first2=Pavel A. \|last3=Valueva \|first3=Maria V. \|last4=Bergerman \|first4=Maxim V. \|date=2022 \|title=RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients \|journal=IEEE Access \|volume=10 \|pages=19215–19231 \|doi=10.1109/ACCESS.2022.3151361 \|s2cid=246895876 \|issn=2169-3536\|doi-access=free \|bibcode=2022IEEEA..1019215N }}</ref> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.		The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<ref>{{Cite journal \|last1=Alcaín \|first1=Eduardo \|last2=Fernández \|first2=Pedro R. \|last3=Nieto \|first3=Rubén \|last4=Montemayor \|first4=Antonio S. \|last5=Vilas \|first5=Jaime \|last6=Galiana-Bordera \|first6=Adrian \|last7=Martinez-Girones \|first7=Pedro Miguel \|last8=Prieto-de-la-Lastra \|first8=Carmen \|last9=Rodriguez-Vila \|first9=Borja \|last10=Bonet \|first10=Marina \|last11=Rodriguez-Sanchez \|first11=Cristina \|date=2021-12-15 \|title=Hardware Architectures for Real-Time Medical Imaging \|journal=Electronics \|language=en \|volume=10 \|issue=24 \|pages=3118 \|doi=10.3390/electronics10243118 \|issn=2079-9292\|doi-access=free }}</ref><ref>{{Cite journal \|last1=Nagornov \|first1=Nikolay N. \|last2=Lyakhov \|first2=Pavel A. \|last3=Valueva \|first3=Maria V. \|last4=Bergerman \|first4=Maxim V. \|date=2022 \|title=RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients \|journal=IEEE Access \|volume=10 \|pages=19215–19231 \|doi=10.1109/ACCESS.2022.3151361 \|s2cid=246895876 \|issn=2169-3536\|doi-access=free \|bibcode=2022IEEEA..1019215N }}</ref> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.

	Another trend in the use of FPGAs is [[hardware acceleration]], where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engine [[Bing (search engine)\|Bing]] is noted for adopting FPGA acceleration for its search algorithm in 2014.<ref name="BingFPGA">{{cite news \|last1=Morgan \|first1=Timothy Pricket \|title=How Microsoft Is Using FPGAs To Speed Up Bing Search \|url=https://www.enterprisetech.com/2014/09/03/microsoft-using-fpgas-speed-bing-search/ \|access-date=2018-09-18 \|publisher=Enterprise Tech \|date=2014-09-03}}</ref> {{as of\|2018}}, FPGAs are seeing increased use as [[AI accelerator]]s including Microsoft's Project Catapult<ref name="ProjCatapult">{{cite web\|url=https://www.microsoft.com/en-us/research/project/project-catapult/\|title=Project Catapult\|date=July 2018\|website=Microsoft Research}}</ref> and for accelerating [[artificial neural network]]s for [[machine learning]] applications.		Another trend in the use of FPGAs is [[hardware acceleration]], where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engine [[Bing (search engine)\|Bing]] is noted for adopting FPGA acceleration for its search algorithm in 2014.<ref name="BingFPGA">{{cite news \|last1=Morgan \|first1=Timothy Pricket \|title=How Microsoft Is Using FPGAs To Speed Up Bing Search \|url=https://www.enterprisetech.com/2014/09/03/microsoft-using-fpgas-speed-bing-search/ \|access-date=2018-09-18 \|publisher=Enterprise Tech \|date=2014-09-03 }}{{Dead link\|date=April 2025 \|bot=InternetArchiveBot \|fix-attempted=yes }}</ref> {{as of\|2018}}, FPGAs are seeing increased use as [[AI accelerator]]s including Microsoft's Project Catapult<ref name="ProjCatapult">{{cite web\|url=https://www.microsoft.com/en-us/research/project/project-catapult/\|title=Project Catapult\|date=July 2018\|website=Microsoft Research}}</ref> and for accelerating [[artificial neural network]]s for [[machine learning]] applications.

	Originally,{{When\|date=October 2018}} FPGAs were reserved for specific [[vertical application]]s where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.{{cn\|date=December 2024}}		Originally,{{When\|date=October 2018}} FPGAs were reserved for specific [[vertical application]]s where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.{{cn\|date=December 2024}}