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AI Driven Design Automation is the use of artificial intelligence (AI) to automate and improve different parts of the electronic design automation (EDA) process. This applies especially to designing integrated circuits (chips) and complex electronic systems. This field has become important because it can help solve the growing problems of complexity, high costs, and the need to release products faster in the semiconductor industry. AI Driven Design Automation uses several methods, including machine learning, expert systems, and reinforcement learning. These are used for many tasks, from planning a chip's architecture and logic synthesis to its physical design and final verification. This article covers the history of AI in EDA, explains its main methods, discusses important applications, and looks at how it affects chip design and the semiconductor industry.

History

1980s–1990s: Expert systems and early experiments

Using AI for design automation started becoming popular in the 1980s and 1990s, mainly with the creation of expert systems. These systems tried to capture the knowledge and practical rules of human design experts. They used a set of rules and reasoning engines to direct the design process.^[2]

A notable early project was the ULYSSES system from Carnegie Mellon University. ULYSSES was a CAD tool integration environment that let expert designers turn their design methods into scripts that could be run automatically. It treated design tools as sources of knowledge that a scheduler could manage.^[3] The ADAM (Advanced Design AutoMation) system at the University of Southern California used an expert system called the Design Planning Engine. This engine figured out design strategies on the fly and handled different design jobs by organizing specialized knowledge into structured formats called frames.^[4]

Other systems like DAA (Design Automation Assistant) showed how to use approaches based on rules for specific jobs, such as register transfer level (RTL) design for systems like the IBM 370.^[2] Research at Carnegie Mellon University also created TALIB, an expert system for mask layout that used over 1200 rules, and EMUCS/DAA, for CPU architectural design with about 70 rules. These projects showed that AI worked better for problems where a few rules could handle a lot of data.^[5] At the same time, tools called silicon compilers like MacPitts, Arsenic, and Palladio appeared. They used algorithms and search techniques to explore different design possibilities. This was another way to automate design, even if it was not always based on expert systems.^[5] Early tests with neural networks in VLSI design also happened during this time, although they were not as common as systems based on rules.

2000s: Introduction of machine learning

In the 2000s, interest in AI for design automation came back. This was mostly because of better machine learning (ML) algorithms and more available data from design and manufacturing. ML methods started being used for complex problems. For example, they were used to model and reduce the effects of small manufacturing differences in semiconductor devices. This became very important as the size of components on chips became smaller. The large amount of data created during chip design provided the foundation needed to train smarter ML models. This allowed for predicting outcomes and optimizing in areas that were hard to automate before.

2016–2020: Reinforcement learning and large scale initiatives

A major turning point happened in the mid to late 2010s, sparked by successes in other areas of AI. The success of DeepMind's AlphaGo in mastering the game of Go inspired researchers. They began to apply reinforcement learning (RL) to difficult EDA problems. These problems often require searching through many options and making a series of decisions.

In 2018, the U.S. DARPA started the Intelligent Design of Electronic Assets (IDEA) program. A main goal of IDEA was to create a fully automated layout generator that required no human intervention. It needed to produce a chip design ready for manufacturing from RTL specifications in 24 hours.^[6] The OpenROAD project, a large effort under IDEA led by UC San Diego with industry and university partners, aimed to build an open source, independent toolchain. It used machine learning, searching multiple options at once, and breaking down big problems into smaller ones to meet its goals.^[6]

A clear demonstration of RL's potential came from Google researchers between 2020 and 2021. They created a deep reinforcement learning method for planning the layout of a chip, known as floorplanning. They reported that this method created layouts that were as good as or better than those made by human experts, and it did so in less than six hours.^[7] This method used a type of network called a graph convolutional neural network. It showed that it could learn general patterns that could be applied to new problems, getting better as it saw more chip designs. The technology was later used to design Google's Tensor Processing Unit (TPU) accelerators.^[7]

2020s: Autonomous systems and agents

Entering the 2020s, the industry saw the commercial launch of autonomous AI driven EDA systems. For example, Synopsys launched DSO.ai™ (Design Space Optimization AI) in early 2020, calling it the first autonomous artificial intelligence application for chip design in the industry.^[8]^[9] This system uses reinforcement learning to search for the best ways to optimize a design within the huge number of possible solutions, trying to improve power, performance, and area (PPA).^[9] By 2023, DSO.ai had been used in over 100 commercial chip productions, which showed that the industry was widely adopting it.^[10] Synopsys later grew its AI tools into a suite called Synopsys.ai. The goal was to use AI in the entire EDA workflow, including verification and testing.^[11]^[12]

These advancements, which combine modern AI methods with cloud computing and large data resources, have led to talks about a new phase in EDA. Industry experts and participants sometimes call this 'EDA 4.0'.^[13]^[14] This new era is defined by the widespread use of AI and machine learning to deal with growing design complexity, automate more of the design process, and help engineers handle the huge amounts of data that EDA tools create.^[13]^[15] The purpose of EDA 4.0 is to optimize product performance, get products to market faster, and make development and manufacturing smoother through intelligent automation.^[14]

AI methods

People are using Artificial intelligence techniques more and more to solve difficult problems in electronic design automation. These methods look at large amounts of design data, learn complex patterns, and automate decisions. The goal is to improve the quality of designs, make the design process faster, and handle the increasing complexity of making semiconductors. Important approaches include supervised learning, unsupervised learning, reinforcement learning, and generative AI.

Supervised learning

Supervised learning is a type of machine learning where algorithms learn from data that is already labeled.^[16] This means every piece of input data in the training set has a known correct answer or "label."^[17] The algorithm learns to connect inputs to outputs by finding the patterns and connections in the training data.^[18] After it is trained, the model can then make predictions on new data it has not seen before.^[19]

In electronic design automation, supervised learning is useful for tasks where past data can predict future results or spot certain problems. This includes estimating design metrics like performance, power, and timing. For example, Ithemal estimates CPU performance,^[20] PRIMAL predicts power use at the RTL stage,^[21] and other methods predict timing delays in circuits by analyzing their structure.^[22]^[23] It is also used to classify parts of a design to find potential problems, like lithography hotspots^[24] or predicting how easy a design will be to route.^[25] Learning circuit representations that are aware of their function also often uses supervised methods.^[26]

Unsupervised learning

Unsupervised learning involves training algorithms on data without any labels. This lets the models find hidden patterns, structures, or connections in the data by themselves.^[27] Common tasks are clustering (which groups similar data together), dimensionality reduction (which reduces the number of variables but keeps important information), and association rule mining (which finds relationships between variables).^[28]

In EDA, these methods are valuable for looking through complex design data to find insights that are not obvious. For instance, clustering can group design settings or tool configurations, which helps in automatically tuning the design process, as seen in the FIST tool.^[29] A major use is in representation learning, where the aim is to automatically learn useful and often simpler representations (features or embeddings) of circuit data. This could involve learning embeddings for analog circuit structures using methods based on graphs^[30] or understanding the function of netlists through contrastive learning methods.^[31]

Reinforcement learning

Reinforcement learning (RL) is a kind of machine learning where an agent, or a computer program, learns to make the best decisions by trying things out in a simulated environment. The agent takes actions, moves between different states, and gets rewards or penalties as feedback. The main goal is to get the highest total reward over time.^[32] RL is different from supervised learning because it does not need labeled data. It also differs from unsupervised learning because it learns by trial and error to achieve a specific goal.^[33]

In EDA, RL is especially good for tasks that require making a series of decisions to find the best solution in very complex situations with many variables. Its adoption by commercial EDA products shows its growing importance.^[34] RL has been used for physical design problems like chip floorplanning. In this task, an agent learns to place blocks to improve things like wire length and performance.^[35]^[36] In logic synthesis, RL can guide how optimization steps are chosen and in what order they are applied to get better results, as seen in methods like AlphaSyn.^[37] Adjusting the size of gates to optimize timing is another area where RL agents can learn effective strategies.^[38]

Generative AI

Generative AI means artificial intelligence models that can create new content, like text, images, or code, instead of just analyzing or working with existing data.^[39] These models learn the underlying patterns and structures from the data they are trained on. They then use this knowledge to create new and original outputs.^[40]

In EDA, generative AI is being used in many ways, especially through Large Language Models (LLMs) and other architectures like Generative Adversarial Networks (GANs).

Large language models (LLMs)

Large Language Models are deep learning models, often based on the transformer architecture. They are pre trained on huge amounts of text and code.^[41] They are very good at understanding, summarizing, creating, and predicting human language and programming languages.^[42]

Their abilities are being used in EDA for jobs such as:

RTL Code Generation: LLMs are used to automatically write code in a Hardware Description Language (HDL) based on written instructions or requirements. Benchmarks like VerilogEval^[43] and RTLLM^[44] have been created to check these abilities, and tools like AutoChip aim to automate this process.^[45]

EDA Script Generation and Tool Interaction: Agents based on LLMs, like ChatEDA, can turn plain language commands into runnable scripts for controlling EDA tools. This could make complex workflows simpler.^[46]

Architectural Design and Exploration: LLMs help in the early stages of design. They can generate high level synthesis code (for example, GPT4AIGChip^[47]), explore design options for special hardware like Compute in Memory accelerators,^[48] or help create and review design requirements (for example, SpecLLM^[49]).

Verification Assistance: Researchers are looking into using LLMs to create verification parts like SystemVerilog Assertions (SVAs) from plain language descriptions.

Other generative models

Besides LLMs, other generative models like Generative Adversarial Networks (GANs) are also used in EDA. A GAN has two neural networks, a generator and a discriminator, which are trained in a competition against each other.^[50] The generator learns to make data samples that look like the training data, while the discriminator learns to tell the difference between real and generated samples.^[51]

In physical design, GANs have been used for tasks like creating sub resolution assist features (SRAFs) to make chips easier to manufacture in lithography (GAN SRAF^[52]) and for optimizing masks (GAN OPC^[53]).

Applications

Artificial intelligence (AI) is being used in many stages of the electronic design workflow. It aims to improve efficiency, get better results, and handle the growing complexity of modern integrated circuits.^[54] ^[55] ^[1] AI helps designers from the very first ideas about architecture all the way to manufacturing and testing.

High level synthesis and architectural exploration

In the first phases of chip design, AI helps with High Level Synthesis (HLS) and exploring different system level design options (DSE). These processes are key for turning general ideas into detailed hardware plans.^[54] AI algorithms, often using supervised learning, are used to build simpler, substitute models. These models can quickly guess important design measurements like area, performance, and power for many different architectural options or HLS settings.^[54]^[1] Being able to guess quickly reduces the need for lengthy simulations. This allows for exploring a wider range of possible designs.^[54] For example, the Ithemal tool uses deep neural networks to estimate how fast basic code blocks will run, which helps in making processor architecture decisions.^[20] Similarly, PRIMAL uses machine learning for guessing power use at the register transfer level (RTL), giving early information about how much power the chip will use.^[21] Reinforcement learning (RL) and Bayesian optimization are also used to guide the DSE process. They help search through the many parameters to find the best HLS settings or architectural details like cache sizes.^[54]^[55] LLMs are also being tested for creating architectural plans or initial C code for HLS, as seen with GPT4AIGChip.^[47]^[1]

Logic synthesis and optimization

Logic synthesis is the process of changing a high level hardware description into an optimized list of electronic gates, known as a gate level netlist, that is ready for a specific manufacturing process. AI methods help with different parts of this process, including logic optimization, technology mapping, and making improvements after mapping.^[54]^[55] Supervised learning, especially with Graph Neural Networks (GNNs) which are good at handling data that looks like a circuit diagram, helps create models to predict design properties like power or error rates in approximate circuits.^[54]^[1] These predictions then guide the optimization algorithms. Reinforcement learning is used to perform logic optimization directly. For example, agents are trained to choose a series of logic changes to reduce area while meeting timing goals.^[54]^[1] AlphaSyn uses Monte Carlo Tree Search with RL to optimize logic for smaller area.^[37] FlowTune uses a multi armed bandit strategy to choose synthesis flows.^[1] AI can also adjust parameters for entire synthesis flows, learning from old designs to recommend the best tool settings for new ones.^[54]

Physical design

Physical design turns the list of electronic gates into a physical layout. This layout defines exactly where each component goes and how they are all connected. AI is used a lot in this area to improve PPA metrics.^[54]^[55]

Placement

Placement is the task of finding the best spots for large circuit blocks, called macros, and smaller standard cells. Reinforcement learning has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing, as shown by Google's research^[35] and the GoodFloorplan method.^[36] Supervised learning models, including CNNs that treat the layout like a picture, are used to predict routing problems like DRVs (e.g., RouteNet^[25]) or timing after routing directly from the placement information.^[54]^[1] RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.^[38]

Clock network synthesis

AI helps in Clock Tree Synthesis (CTS) by optimizing the network that distributes the clock signal. GANs, sometimes used with RL (e.g., GAN CTS), are used to predict and improve clock tree structures. The goal is to reduce clock skew and power use.^[54]^[55]^[56]

Routing

Routing creates the physical wire connections. AI models predict routing traffic jams using methods like GANs to help guide the routing algorithms.^[54]^[1] RL is also used to optimize the order in which wires are routed to reduce errors.^[54]

Power/ground network synthesis and analysis

AI models, including CNNs and tree based methods, help in designing and analyzing the Power Delivery Network (PDN). They do this by quickly estimating static and dynamic IR drop. This guides the creation of the PDN and reduces the number of design cycles.^[54]^[55]^[1]

Verification and validation

Verification and validation are very important to make sure a chip works correctly. AI is used to make these processes, which often take a long time, more efficient.^[54] LLMs are used to turn plain language requirements into formal SystemVerilog assertions (SVAs) (e.g., AssertLLM)^[1] and to help with security verification.^[1] Methods for predicting timing analysis results based on circuit structure, like those first developed by Kahng et al.^[22] and improved with transformer models like TF Predictor,^[23] make the final timing checks much faster. DeepGate2 provides a way to learn circuit representations that understand function, which can help with verification tasks.^[26]

Analog and mixed signal design

AI methods are being used more often in the complex field of analog and mixed signal circuit design. They are helping to choose the circuit structure, determine the size of components, and automate the layout.^[54]^[1] AI models, including Variational Autoencoders (VAEs) and RL, help to explore and create new circuit structures.^[1] For instance, graph embeddings can be used to optimize the structure of operational amplifiers.^[30] Machine learning substitute models give fast performance estimates for component sizing, while RL directly optimizes the component parameters.^[1]^[54]

Test, manufacturing and yield optimization

AI helps in the stages after the silicon chip is made, including testing, design for manufacturability (DFM), and improving the production yield.^[54] In lithography, AI models like CNNs and GANs are used for SRAF generation (e.g., GAN SRAF^[52]) and OPC (e.g., GAN OPC^[53]) to improve how well the chip prints. AI also predicts lithography problems, known as hotspots, from the layout, as shown by Yang et al.^[24] For tuning the broader design flow for manufacturing, FIST uses tree based methods to select parameters.^[29]

Hardware-software co-design

Hardware-Software Co-design is about optimizing the hardware and software parts of a system at the same time. LLMs are starting to be used as tools to help with this. For example, they help in designing Compute in Memory (CiM) DNN accelerators, where how the software is arranged and how the hardware is set up are closely connected, as explored by Yan et al.^[48]^[56] LLMs can also create architectural plans (e.g., SpecLLM^[49]) or HDL code using benchmarks like VerilogEval^[43] and RTLLM,^[44] or with tools like AutoChip.^[45] Additionally, agents based on LLMs like ChatEDA make it easier to interact with EDA tools for different design stages.^[46] For netlist representation, work by Wang et al. focuses on learning embeddings that understand the function of the circuit.^[31]

Industry adoption and ecosystem

The use of artificial intelligence in electronic design automation is a widespread trend. Many different players in the semiconductor world are helping to create and use these technologies. This includes companies that sell EDA tools and develop software with AI, semiconductor design companies and foundries that use these tools to make and manufacture chips, and very large technology companies that might design their own chips using AI driven methods.

EDA tool vendors

Major EDA companies are leading the way in adding AI to their tool suites to handle growing design complexity. Their strategies often involve creating complete AI platforms. These platforms use machine learning in many different steps of the design and manufacturing process.

Synopsys provides a set of tools in its Synopsys.ai initiative. This initiative aims to improve design metrics and productivity from the system architecture stage all the way to manufacturing.^[12] A main component uses reinforcement learning to improve power, performance, and area (PPA) during the process that goes from the initial design description to the final manufacturing file (DSO.ai). Other parts use AI to speed up verification, optimize test pattern generation for manufacturing, and improve the design of analog circuits in different conditions.^[12]

Cadence has created its Cadence.AI platform. The company says it uses "agentic AI workflows" to cut down on the design engineering time for complex SoCs.^[57] Key platforms use AI to optimize the digital design flow (Cadence Cerebrus), improve verification productivity (Verisium), design custom and analog ICs (Virtuoso Studio), and analyze systems at a high level (Optimality Intelligent System Explorer).^[57]^[58]

Siemens EDA directs its AI strategy at improving its current software engines and workflows to give engineers better design insights.^[59] AI is used inside its Calibre platform to speed up manufacturing tasks like Design for Manufacturability (DFM), Resolution Enhancement Techniques (RET), and Optical Proximity Correction (OPC). AI is also used in its Questa suite to close coverage faster in digital verification and in its Solido suite to lessen the characterization work for analog designs.^[59]

Semiconductor design and FPGA companies

Companies that design semiconductor chips, like FPGAs and adaptive SoCs, are major users and creators of EDA methods that are improved with AI to make their design processes more efficient.

AMD offers a suite of tools for its adaptive hardware that uses AI ideas. The AMD Vitis platform is an environment for developing designs on its SoCs and FPGAs. It includes a component, Vitis AI, which has libraries and pre trained models to speed up AI inference.^[60]^[61] The related Vivado Design Suite uses machine learning methods to improve the quality of results (QoR) and help with achieving timing goals and estimating power for the hardware design.^[60]

NVIDIA has a specific Design Automation Research group to look into new EDA methods.^[62] The group focuses on EDA tools that are accelerated by GPUs and using AI methods like Bayesian optimization and reinforcement learning for EDA problems. One example of their research is AutoDMP, a tool that automates macro placement using multi objective Bayesian optimization and a GPU accelerated placer.^[63]

Cloud providers and hyperscalers

Large cloud service providers and hyperscale companies have two main roles. They provide the powerful and flexible computing power needed to run difficult AI and EDA tasks, and many also design their own custom silicon, often using AI in their internal design processes.

Google Cloud, for example, provides a platform that supports EDA workloads with flexible computing resources, special storage solutions, and high speed networking.^[64] At the same time, Google's internal chip design teams have contributed to EDA research, especially by using reinforcement learning for physical design tasks like chip floorplanning.^[35]

IBM provides infrastructure on its cloud platform that is focused on EDA, with a strong emphasis on secure environments for foundries and high performance computing.^[65] Their solutions include high performance parallel storage and tools for managing large scale jobs. These are designed to help design houses manage the complex simulation and modeling tasks that are part of modern EDA.^[65]

Limitations and challenges

Data quality and availability

A main challenge for using AI effectively in EDA is the availability and quality of data.^[54]^[1] Machine learning models, especially deep learning ones, usually need large, varied, and high quality datasets to be trained. This ensures they can work well on new designs they have not seen before.^[1] However, a lot of the detailed design data in the semiconductor industry is secret and very sensitive. This makes companies unwilling to share it.^[54]^[1] This lack of public, detailed examples makes it difficult for university researchers and for the development of models that can be widely used. Even when data is available, it might have problems like being noisy, incomplete, or unbalanced. For instance, having many more examples of successful designs than ones with problems can lead to biased or poorly performing AI models.^[55] The work and cost of collecting, organizing, and correctly labeling large EDA datasets also create big obstacles.^[1] Solving these data related problems is key for moving AI forward in EDA. Possible solutions include creating strong data augmentation methods, generating realistic synthetic data, and building community platforms for sharing data securely and for benchmarking.^[1]

Integration and compute cost

Putting AI solutions into practice in the EDA field has major challenges. These include fitting the AI into the complex sets of tools that already exist and handling the high cost of computing power.^[54]^[55] Adding new AI models and algorithms into established EDA workflows, which are often made of many connected tools and private formats, takes a lot of engineering work and can have problems working with other tools.^[54]^[1] Also, training and running complex AI models, especially deep learning ones, requires a lot of computing resources. This includes powerful GPUs or special AI accelerators, large amounts of memory, and long processing times.^[54]^[1] These needs lead to higher costs for both creating and using the AI models.^[55] Making AI methods able to handle the ever growing size and complexity of modern chip designs, while staying efficient and using a reasonable amount of memory, is still an ongoing challenge.^[55]^[1]

Intellectual property and confidentiality

The use of AI in EDA, especially with sensitive design data, brings up serious worries about protecting secret company information, known as intellectual property (IP), and keeping data private.^[54]^[56] Chip designs are very valuable IP, and there is always a risk when giving this secret information to AI models, particularly if they are made by other companies or run on cloud platforms.^[54] It is extremely important to make sure that design data used for training or making decisions is not compromised, leaked, or used to accidentally leak secret knowledge.^[56] While strategies like fine tuning open source models on private data are being tried to reduce some privacy risks,^[56] it is essential to set up secure data handling rules, strong access controls, and clear data management policies. The unwillingness to share detailed design data because of these IP and privacy worries also slows down collaborative research and the creation of better AI models for the EDA industry.^[54]^[56]

Human oversight and interpretability

Even with the push for more automation, the role of human designers is still vital, and making AI models understandable continues to be a challenge.^[54]^[1] Many advanced AI models, especially deep learning systems, can act like "black boxes," which makes it hard for engineers to understand why they make certain predictions or design choices.^[54] This lack of clarity can prevent adoption, as designers might not want to trust or use solutions if their decision making process is not clear, especially in critical applications or when fixing unexpected problems.^[55] While AI can automate many jobs, human knowledge is still essential. It is needed to set design goals, check the results from AI, handle new or unusual situations where AI might fail, and provide the specialized knowledge that often guides AI development.^[54]^[1] To effectively use AI in EDA, it means that human engineers and smart tools need to work together effectively. This requires designers to learn new skills for working with and supervising AI systems.^[1]

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Cite error: A list-defined reference named "DefReinforcementLearningGoogle" is not used in the content (see the help page).
Cite error: A list-defined reference named "SynopsysAIBrochure" is not used in the content (see the help page).

External links

The OpenROAD Project – Official website for the open-source autonomous layout generator.

Design Automation Conference (DAC) – Premier academic and industry conference for EDA.

Category:Electronic design automation Category:Applications of artificial intelligence Category:Semiconductor device fabrication Category:Integrated circuits

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[Cao2022TFpredictor-23] Cao, Peng; He, Guoqing; Yang, Tai (2023-07). "TF-Predictor: Transformer-Based Prerouting Path Delay Prediction Framework". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42 (7): 2227–2237. doi:10.1109/TCAD.2022.3216752. ISSN 1937-4151. {{cite journal}}: Check date values in: |date= (help)

[Yang2017Hotspot-24] Yang, Haoyu; Luo, Luyang; Su, Jing; Lin, Chenxi; Yu, Bei. "Imbalance aware lithography hotspot detection: a deep learning approach". SPIE Digital Library. doi:10.1117/1.jmm.16.3.033504.short.

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[Shi2023DeepGate2-26] Shi, Zhengyuan; Pan, Hongyang; Khan, Sadaf; Li, Min; Liu, Yi; Huang, Junhua; Zhen, Hui-Ling; Yuan, Mingxuan; Chu, Zhufei; Xu, Qiang (2023-10). "DeepGate2: Functionality-Aware Circuit Representation Learning". 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD): 1–9. doi:10.1109/ICCAD57390.2023.10323798. {{cite journal}}: Check date values in: |date= (help)

[DefUnsupervisedLearningAWS-27] "What Is Unsupervised Learning? | IBM". www.ibm.com. 23 September 2021. Retrieved 14 June 2025.

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[Xie2020Fist-29] Xie, Zhiyao; Fang, Guan-Qi; Huang, Yu-Hung; Ren, Haoxing; Zhang, Yanqing; Khailany, Brucek; Fang, Shao-Yun; Hu, Jiang; Chen, Yiran; Barboza, Erick Carvajal (2020-01). "FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning". 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC): 19–25. doi:10.1109/ASP-DAC47756.2020.9045201. {{cite journal}}: Check date values in: |date= (help)

[Lu2022AnalogTopologyOpt-30] Lu, Jialin; Lei, Liangbo; Yang, Fan; Shang, Li; Zeng, Xuan (2022-03). "Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding". 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE): 142–147. doi:10.23919/DATE54114.2022.9774676. {{cite journal}}: Check date values in: |date= (help)

[Wang2022NetlistFunctionality-31] Wang, Ziyi; Bai, Chen; He, Zhuolun; Zhang, Guangliang; Xu, Qiang; Ho, Tsung-Yi; Yu, Bei; Huang, Yu (23 August 2022). "Functionality matters in netlist representation learning". Proceedings of the 59th ACM/IEEE Design Automation Conference. DAC '22. New York, NY, USA: Association for Computing Machinery: 61–66. doi:10.1145/3489517.3530410. ISBN 978-1-4503-9142-9.

[DefReinforcementLearningMicrosoft-32] "Reinforcement Learning". GeeksforGeeks. 25 April 2018. Retrieved 14 June 2025.

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[Mirhoseini2021Floorplanning-35] Mirhoseini, Azalia; Goldie, Anna; Yazgan, Mustafa; Jiang, Joe Wenjie; Songhori, Ebrahim; Wang, Shen; Lee, Young-Joon; Johnson, Eric; Pathak, Omkar; Nova, Azade; Pak, Jiwoo; Tong, Andy; Srinivasa, Kavya; Hang, William; Tuncer, Emre (2021-06). "A graph placement methodology for fast chip design". Nature. 594 (7862): 207–212. doi:10.1038/s41586-021-03544-w. ISSN 1476-4687. {{cite journal}}: Check date values in: |date= (help)

[Xu2021GoodFloorplan-36] Xu, Qi; Geng, Hao; Chen, Song; Yuan, Bo; Zhuo, Cheng; Kang, Yi; Wen, Xiaoqing (2022-10). "GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41 (10): 3492–3502. doi:10.1109/TCAD.2021.3131550. ISSN 1937-4151. {{cite journal}}: Check date values in: |date= (help)

[Pei2023AlphaSyn-37] Pei, Zehua; Liu, Fangzhou; He, Zhuolun; Chen, Guojin; Zheng, Haisheng; Zhu, Keren; Yu, Bei (2023-10). "AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search". 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD): 1–9. doi:10.1109/ICCAD57390.2023.10323856. {{cite journal}}: Check date values in: |date= (help)

[Lu2021RLSizer-38] Lu, Yi-Chen; Nath, Siddhartha; Khandelwal, Vishal; Lim, Sung Kyu (2021-12). "RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning". 2021 58th ACM/IEEE Design Automation Conference (DAC): 733–738. doi:10.1109/DAC18074.2021.9586138. {{cite journal}}: Check date values in: |date= (help)

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[Lu2024RTLLM-44] Lu, Yao; Liu, Shang; Zhang, Qijun; Xie, Zhiyao (2024-01). "RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model". 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC): 722–727. doi:10.1109/ASP-DAC58780.2024.10473904. {{cite journal}}: Check date values in: |date= (help)

[Thakur2023AutoChip-45] Thakur, Shailja; Blocklove, Jason; Pearce, Hammond; Tan, Benjamin; Garg, Siddharth; Karri, Ramesh (4 June 2024), AutoChip: Automating HDL Generation Using LLM Feedback, arXiv, doi:10.48550/arXiv.2311.04887, arXiv:2311.04887, retrieved 14 June 2025

[Wu2024ChatEDA-46] Wu, Haoyuan; He, Zhuolun; Zhang, Xinyun; Yao, Xufeng; Zheng, Su; Zheng, Haisheng; Yu, Bei (2024-10). "ChatEDA: A Large Language Model Powered Autonomous Agent for EDA". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43 (10): 3184–3197. doi:10.1109/TCAD.2024.3383347. ISSN 1937-4151. {{cite journal}}: Check date values in: |date= (help)

[Fu2023GPT4AIGChip-47] Fu, Yonggan; Zhang, Yongan; Yu, Zhongzhi; Li, Sixu; Ye, Zhifan; Li, Chaojian; Wan, Cheng; Lin, Yingyan Celine (2023-10). "GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models". 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD): 1–9. doi:10.1109/ICCAD57390.2023.10323953. {{cite journal}}: Check date values in: |date= (help)

[Yan2023LLMsForCiM-48] Yan, Zheyu; Qin, Yifan; Hu, Xiaobo Sharon; Shi, Yiyu (2023-09). "On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators". 2023 IEEE 36th International System-on-Chip Conference (SOCC): 1–6. doi:10.1109/SOCC58585.2023.10256783. {{cite journal}}: Check date values in: |date= (help)

[Li2024SpecLLM-49] Li, Mengming; Fang, Wenji; Zhang, Qijun; Xie, Zhiyao (24 January 2024). "SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model". arXiv.org. Retrieved 14 June 2025.

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[Alawieh2020GANSRAF-52] Alawieh, Mohamed Baker; Lin, Yibo; Zhang, Zaiwei; Li, Meng; Huang, Qixing; Pan, David Z. (2021-02). "GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40 (2): 373–385. doi:10.1109/TCAD.2020.2995338. ISSN 1937-4151. {{cite journal}}: Check date values in: |date= (help)

[Yang2018GANOPC-53] Yang, Haoyu; Li, Shuhe; Ma, Yuzhe; Yu, Bei; Young, Evangeline F. Y. (24 June 2018). "GAN-OPC: mask optimization with lithography-guided generative adversarial nets". Proceedings of the 55th Annual Design Automation Conference. DAC '18. New York, NY, USA: Association for Computing Machinery: 1–6. doi:10.1145/3195970.3196056. ISBN 978-1-4503-5700-5.

[Rapp2021MLCAD-54] ^ ^a ^b ^c ^d ^e ^f ^g ^h ⁱ ^j ^k ^l ^m ⁿ ^o ^p ^q ^r ^s ^t ^u ^v ^w ^x ^y ^z ^aa ^ab ^ac ^ad Rapp, Martin; Amrouch, Hussam; Lin, Yibo; Yu, Bei; Pan, David Z.; Wolf, Marilyn; Henkel, Jörg (2022-10). "MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41 (10): 3162–3181. doi:10.1109/TCAD.2021.3124762. ISSN 1937-4151. {{cite journal}}: Check date values in: |date= (help)

[Gubbi2022Survey-55] ^ ^a ^b ^c ^d ^e ^f ^g ^h ⁱ ^j ^k Gubbi, Kevin Immanuel; Beheshti-Shirazi, Sayed Aresh; Sheaves, Tyler; Salehi, Soheil; PD, Sai Manoj; Rafatirad, Setareh; Sasan, Avesta; Homayoun, Houman (6 June 2022). "Survey of Machine Learning for Electronic Design Automation". Proceedings of the Great Lakes Symposium on VLSI 2022. GLSVLSI '22. New York, NY, USA: Association for Computing Machinery: 513–518. doi:10.1145/3526241.3530834. ISBN 978-1-4503-9322-5.

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@@ Line 3: / Line 3: @@
 '''AI Driven Design Automation''' is the use of [[artificial intelligence]] (AI) to automate and improve different parts of the [[electronic design automation]] (EDA) process. This applies especially to designing [[integrated circuit]]s (chips) and complex electronic systems. This field has become important because it can help solve the growing problems of complexity, high costs, and the need to release products faster in the [[semiconductor industry]]. AI Driven Design Automation uses several methods, including [[machine learning]], [[expert system]]s, and [[reinforcement learning]]. These are used for many tasks, from planning a chip's architecture and [[logic synthesis]] to its [[physical design (electronics)|physical design]] and final [[verification and validation|verification]]. This article covers the history of AI in EDA, explains its main methods, discusses important applications, and looks at how it affects chip design and the semiconductor industry.
+[[File:EDA Large Circuit Models.png|thumb|This figure explains how can we train large circuit models by making use of the front-end (depicted in blue) and back-end (depicted in yellow) of the EDA flow in order to either enhance existing EDA tools or to create novel EDA applications.<ref name=":0">{{Citation |last=Chen |first=Lei |title=The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models |date=2024-05-01 |url=http://arxiv.org/abs/2403.07257 |access-date=2025-06-14 |publisher=arXiv |doi=10.48550/arXiv.2403.07257 |id=arXiv:2403.07257 |last2=Chen |first2=Yiqi |last3=Chu |first3=Zhufei |last4=Fang |first4=Wenji |last5=Ho |first5=Tsung-Yi |last6=Huang |first6=Ru |last7=Huang |first7=Yu |last8=Khan |first8=Sadaf |last9=Li |first9=Min}}</ref>]]
 ==History==
@@ Line 13: / Line 14: @@
 Other systems like DAA (Design Automation Assistant) showed how to use approaches based on rules for specific jobs, such as [[Register-transfer level|register transfer level]] (RTL) design for systems like the IBM 370.<ref name="ParkerHayati1987"/> Research at Carnegie Mellon University also created TALIB, an expert system for mask layout that used over 1200 rules, and EMUCS/DAA, for CPU architectural design with about 70 rules. These projects showed that AI worked better for problems where a few rules could handle a lot of data.<ref name="Kirk1985"/> At the same time, tools called [[silicon compiler]]s like MacPitts, Arsenic, and Palladio appeared. They used algorithms and search techniques to explore different design possibilities. This was another way to automate design, even if it was not always based on expert systems.<ref name="Kirk1985"/> Early tests with [[artificial neural network|neural networks]] in [[Very Large Scale Integration|VLSI]] design also happened during this time, although they were not as common as systems based on rules.
-===2000s: Introduction of Machine Learning===
+===2000s: Introduction of machine learning===
 In the 2000s, interest in AI for design automation came back. This was mostly because of better [[machine learning]] (ML) algorithms and more available data from design and manufacturing. ML methods started being used for complex problems. For example, they were used to model and reduce the effects of small manufacturing differences in semiconductor devices. This became very important as the size of components on chips became smaller. The large amount of data created during chip design provided the foundation needed to train smarter ML models. This allowed for predicting outcomes and optimizing in areas that were hard to automate before.
-===2016–2020: Reinforcement Learning and Large Scale Initiatives===
+===2016–2020: Reinforcement learning and large scale initiatives===
 A major turning point happened in the mid to late 2010s, sparked by successes in other areas of AI. The success of [[DeepMind]]'s [[AlphaGo]] in mastering the game of [[Go (game)|Go]] inspired researchers. They began to apply [[Reinforcement learning|reinforcement learning (RL)]] to difficult EDA problems. These problems often require searching through many options and making a series of decisions.
@@ Line 23: / Line 24: @@
 A clear demonstration of RL's potential came from Google researchers between 2020 and 2021. They created a deep reinforcement learning method for planning the layout of a chip, known as [[Floorplan (microelectronics)|floorplanning]]. They reported that this method created layouts that were as good as or better than those made by human experts, and it did so in less than six hours.<ref name="MirhoseiniNature2021"/> This method used a type of network called a [[graph neural network|graph convolutional neural network]]. It showed that it could learn general patterns that could be applied to new problems, getting better as it saw more chip designs. The technology was later used to design Google's [[Tensor Processing Unit|Tensor Processing Unit (TPU)]] accelerators.<ref name="MirhoseiniNature2021"/>
-===2020s: Autonomous Systems and Agents===
+===2020s: Autonomous systems and agents===
 Entering the 2020s, the industry saw the commercial launch of autonomous AI driven EDA systems. For example, Synopsys launched DSO.ai™ (Design Space Optimization AI) in early 2020, calling it the first autonomous artificial intelligence application for chip design in the industry.<ref name="SynopsysDSOlaunch2020" /><ref name="SynopsysDSOsite" /> This system uses reinforcement learning to search for the best ways to optimize a design within the huge number of possible solutions, trying to improve power, performance, and area (PPA).<ref name="SynopsysDSOsite" /> By 2023, DSO.ai had been used in over 100 commercial chip productions, which showed that the industry was widely adopting it.<ref name="EETimesDSO mainstream" /> Synopsys later grew its AI tools into a suite called Synopsys.ai. The goal was to use AI in the entire EDA workflow, including verification and testing.<ref name="ForbesSynopsysAIsuite" /><ref name="VirtualGraffitiSynopsysAI" />
 These advancements, which combine modern AI methods with [[cloud computing]] and large data resources, have led to talks about a new phase in EDA. Industry experts and participants sometimes call this 'EDA 4.0'.<ref name="SemiconductorEngineeringEDA4.0" /><ref name="UnipvNewsEDA4.0" /> This new era is defined by the widespread use of AI and machine learning to deal with growing design complexity, automate more of the design process, and help engineers handle the huge amounts of data that EDA tools create.<ref name="SemiconductorEngineeringEDA4.0" /><ref name="EmbeddedAIbasedEDA" /> The purpose of EDA 4.0 is to optimize product performance, get products to market faster, and make development and manufacturing smoother through intelligent automation.<ref name="UnipvNewsEDA4.0" />
-== AI Methods ==
+== AI methods ==
 People are using [[Artificial intelligence]] techniques more and more to solve difficult problems in electronic design automation. These methods look at large amounts of design data, learn complex patterns, and automate decisions. The goal is to improve the quality of designs, make the design process faster, and handle the increasing complexity of making semiconductors. Important approaches include supervised learning, unsupervised learning, reinforcement learning, and generative AI.
-===Supervised Learning===
+===Supervised learning===
 [[Supervised learning]] is a type of machine learning where algorithms learn from data that is already labeled.<ref name="DefSupervisedLearningIBM"/> This means every piece of input data in the training set has a known correct answer or "label."<ref name="DefSupervisedLearningGoogle"/> The algorithm learns to connect inputs to outputs by finding the patterns and connections in the training data.<ref name="DefSupervisedLearningSAS"/> After it is trained, the model can then make predictions on new data it has not seen before.<ref name="DefSupervisedLearningMathWorks"/>
 In electronic design automation, supervised learning is useful for tasks where past data can predict future results or spot certain problems. This includes estimating design metrics like performance, power, and timing. For example, Ithemal estimates CPU performance,<ref name="Mendis2019Ithemal"/> PRIMAL predicts power use at the RTL stage,<ref name="Zhou2019Primal"/> and other methods predict timing delays in circuits by analyzing their structure.<ref name="Kahng2018PBAfromGBA"/><ref name="Cao2022TFpredictor"/> It is also used to classify parts of a design to find potential problems, like lithography hotspots<ref name="Yang2017Hotspot"/> or predicting how easy a design will be to route.<ref name="Xie2018RouteNet"/> Learning circuit representations that are aware of their function also often uses supervised methods.<ref name="Shi2023DeepGate2"/>
-===Unsupervised Learning===
+===Unsupervised learning===
 [[Unsupervised learning]] involves training algorithms on data without any labels. This lets the models find hidden patterns, structures, or connections in the data by themselves.<ref name="DefUnsupervisedLearningAWS"/> Common tasks are clustering (which groups similar data together), dimensionality reduction (which reduces the number of variables but keeps important information), and association rule mining (which finds relationships between variables).<ref name="DefUnsupervisedLearningTechTarget"/>
 In EDA, these methods are valuable for looking through complex design data to find insights that are not obvious. For instance, clustering can group design settings or tool configurations, which helps in automatically tuning the design process, as seen in the FIST tool.<ref name="Xie2020Fist"/> A major use is in representation learning, where the aim is to automatically learn useful and often simpler representations (features or embeddings) of circuit data. This could involve learning embeddings for analog circuit structures using methods based on graphs<ref name="Lu2022AnalogTopologyOpt"/> or understanding the function of netlists through contrastive learning methods.<ref name="Wang2022NetlistFunctionality"/>
-===Reinforcement Learning===
+===Reinforcement learning===
-[[Reinforcement learning]] (RL) is a kind of machine learning where an agent, or a computer program, learns to make the best decisions by trying things out in a simulated environment.<ref name="DefReinforcementLearningGoogle"/> The agent takes actions, moves between different states, and gets rewards or penalties as feedback. The main goal is to get the highest total reward over time.<ref name="DefReinforcementLearningMicrosoft"/> RL is different from supervised learning because it does not need labeled data. It also differs from unsupervised learning because it learns by trial and error to achieve a specific goal.<ref name="DefReinforcementLearningBerkeley"/>
+[[Reinforcement learning]] (RL) is a kind of machine learning where an agent, or a computer program, learns to make the best decisions by trying things out in a simulated environment. The agent takes actions, moves between different states, and gets rewards or penalties as feedback. The main goal is to get the highest total reward over time.<ref name="DefReinforcementLearningMicrosoft"/> RL is different from supervised learning because it does not need labeled data. It also differs from unsupervised learning because it learns by trial and error to achieve a specific goal.<ref name="DefReinforcementLearningBerkeley"/>
 In EDA, RL is especially good for tasks that require making a series of decisions to find the best solution in very complex situations with many variables. Its adoption by commercial EDA products shows its growing importance.<ref name="SynopsysAI2023"/> RL has been used for physical design problems like chip floorplanning. In this task, an agent learns to place blocks to improve things like wire length and performance.<ref name="Mirhoseini2021Floorplanning"/><ref name="Xu2021GoodFloorplan"/> In logic synthesis, RL can guide how optimization steps are chosen and in what order they are applied to get better results, as seen in methods like AlphaSyn.<ref name="Pei2023AlphaSyn"/> Adjusting the size of gates to optimize timing is another area where RL agents can learn effective strategies.<ref name="Lu2021RLSizer"/>
@@ Line 52: / Line 53: @@
 In EDA, generative AI is being used in many ways, especially through Large Language Models (LLMs) and other architectures like Generative Adversarial Networks (GANs).
-====Large Language Models (LLMs)====
+====Large language models (LLMs)====
 [[Large language model|Large Language Models]] are deep learning models, often based on the transformer architecture. They are pre trained on huge amounts of text and code.<ref name="DefLLMAWS"/> They are very good at understanding, summarizing, creating, and predicting human language and programming languages.<ref name="DefLLMNvidia"/>
 Their abilities are being used in EDA for jobs such as:
@@ Line 63: / Line 65: @@
 '''Verification Assistance:''' Researchers are looking into using LLMs to create verification parts like SystemVerilog Assertions (SVAs) from plain language descriptions.
-====Other Generative Models====
+====Other generative models====
 Besides LLMs, other generative models like [[Generative adversarial network|Generative Adversarial Networks]] (GANs) are also used in EDA. A GAN has two neural networks, a generator and a discriminator, which are trained in a competition against each other.<ref name="DefGANOracle"/> The generator learns to make data samples that look like the training data, while the discriminator learns to tell the difference between real and generated samples.<ref name="DefGANAWS"/>
-In physical design, GANs have been used for tasks like creating sub resolution assist features (SRAFs) to make chips easier to manufacture in lithography (GAN SRAF<ref name="Alawieh2020GANSRAF"/>) and for optimizing masks (GAN OPC<ref name="Yang2018GANOPC"/>).
+In physical design, GANs have been used for tasks like creating sub resolution assist features (SRAFs) to make chips easier to manufacture in lithography (GAN SRAF<ref name="Alawieh2020GANSRAF" />) and for optimizing masks (GAN OPC<ref name="Yang2018GANOPC" />).
 == Applications ==
-Artificial intelligence (AI) is being used in many stages of the electronic design workflow. It aims to improve efficiency, get better results, and handle the growing complexity of modern integrated circuits.<ref name="Rapp2021MLCAD"/> <ref name="Gubbi2022Survey"/> <ref name="Chen2024AINativeEDA"/> AI helps designers from the very first ideas about architecture all the way to manufacturing and testing.
+Artificial intelligence (AI) is being used in many stages of the electronic design workflow. It aims to improve efficiency, get better results, and handle the growing complexity of modern integrated circuits.<ref name="Rapp2021MLCAD"/> <ref name="Gubbi2022Survey"/> <ref name=":0" /> AI helps designers from the very first ideas about architecture all the way to manufacturing and testing.
-===High Level Synthesis and Architectural Exploration===
+===High level synthesis and architectural exploration===
-In the first phases of chip design, AI helps with [[High-level synthesis|High Level Synthesis (HLS)]] and exploring different system level design options (DSE). These processes are key for turning general ideas into detailed hardware plans.<ref name="Rapp2021MLCAD"/> AI algorithms, often using [[Supervised learning|supervised learning]], are used to build simpler, substitute models. These models can quickly guess important design measurements like area, performance, and power for many different architectural options or HLS settings.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> Being able to guess quickly reduces the need for lengthy simulations. This allows for exploring a wider range of possible designs.<ref name="Rapp2021MLCAD"/> For example, the Ithemal tool uses deep neural networks to estimate how fast basic code blocks will run, which helps in making processor architecture decisions.<ref name="Mendis2019Ithemal"/> Similarly, PRIMAL uses machine learning for guessing power use at the register transfer level (RTL), giving early information about how much power the chip will use.<ref name="Zhou2019Primal"/> [[Reinforcement learning|Reinforcement learning (RL)]] and [[Bayesian optimization]] are also used to guide the DSE process. They help search through the many parameters to find the best HLS settings or architectural details like cache sizes.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/> LLMs are also being tested for creating architectural plans or initial C code for HLS, as seen with GPT4AIGChip.<ref name="Fu2023GPT4AIGChip"/><ref name="Chen2024AINativeEDA"/>
+In the first phases of chip design, AI helps with [[High-level synthesis|High Level Synthesis (HLS)]] and exploring different system level design options (DSE). These processes are key for turning general ideas into detailed hardware plans.<ref name="Rapp2021MLCAD"/> AI algorithms, often using [[Supervised learning|supervised learning]], are used to build simpler, substitute models. These models can quickly guess important design measurements like area, performance, and power for many different architectural options or HLS settings.<ref name="Rapp2021MLCAD"/><ref name=":0" /> Being able to guess quickly reduces the need for lengthy simulations. This allows for exploring a wider range of possible designs.<ref name="Rapp2021MLCAD"/> For example, the Ithemal tool uses deep neural networks to estimate how fast basic code blocks will run, which helps in making processor architecture decisions.<ref name="Mendis2019Ithemal"/> Similarly, PRIMAL uses machine learning for guessing power use at the register transfer level (RTL), giving early information about how much power the chip will use.<ref name="Zhou2019Primal"/> [[Reinforcement learning|Reinforcement learning (RL)]] and [[Bayesian optimization]] are also used to guide the DSE process. They help search through the many parameters to find the best HLS settings or architectural details like cache sizes.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/> LLMs are also being tested for creating architectural plans or initial C code for HLS, as seen with GPT4AIGChip.<ref name="Fu2023GPT4AIGChip"/><ref name=":0" />
-===Logic Synthesis and Optimization===
+===Logic synthesis and optimization===
-[[Logic synthesis]] is the process of changing a high level hardware description into an optimized list of electronic gates, known as a [[Netlist|gate level netlist]], that is ready for a specific manufacturing process. AI methods help with different parts of this process, including logic optimization, technology mapping, and making improvements after mapping.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/> Supervised learning, especially with [[Graph neural network|Graph Neural Networks (GNNs)]] which are good at handling data that looks like a circuit diagram, helps create models to predict design properties like power or error rates in approximate circuits.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> These predictions then guide the optimization algorithms. Reinforcement learning is used to perform logic optimization directly. For example, agents are trained to choose a series of logic changes to reduce area while meeting timing goals.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> AlphaSyn uses Monte Carlo Tree Search with RL to optimize logic for smaller area.<ref name="Pei2023AlphaSyn"/> FlowTune uses a multi armed bandit strategy to choose synthesis flows.<ref name="Chen2024AINativeEDA"/> AI can also adjust parameters for entire synthesis flows, learning from old designs to recommend the best tool settings for new ones.<ref name="Rapp2021MLCAD"/>
+[[Logic synthesis]] is the process of changing a high level hardware description into an optimized list of electronic gates, known as a [[Netlist|gate level netlist]], that is ready for a specific manufacturing process. AI methods help with different parts of this process, including logic optimization, technology mapping, and making improvements after mapping.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/> Supervised learning, especially with [[Graph neural network|Graph Neural Networks (GNNs)]] which are good at handling data that looks like a circuit diagram, helps create models to predict design properties like power or error rates in approximate circuits.<ref name="Rapp2021MLCAD"/><ref name=":0" /> These predictions then guide the optimization algorithms. Reinforcement learning is used to perform logic optimization directly. For example, agents are trained to choose a series of logic changes to reduce area while meeting timing goals.<ref name="Rapp2021MLCAD"/><ref name=":0" /> AlphaSyn uses Monte Carlo Tree Search with RL to optimize logic for smaller area.<ref name="Pei2023AlphaSyn"/> FlowTune uses a multi armed bandit strategy to choose synthesis flows.<ref name=":0" /> AI can also adjust parameters for entire synthesis flows, learning from old designs to recommend the best tool settings for new ones.<ref name="Rapp2021MLCAD"/>
-===Physical Design===
+===Physical design===
 [[Physical design (electronics)|Physical design]] turns the list of electronic gates into a physical layout. This layout defines exactly where each component goes and how they are all connected. AI is used a lot in this area to improve PPA metrics.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/>
 ====Placement====
-[[Place and route#Placement|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller standard cells. Reinforcement learning has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing, as shown by Google's research<ref name="Mirhoseini2021Floorplanning"/> and the GoodFloorplan method.<ref name="Xu2021GoodFloorplan"/> Supervised learning models, including [[Convolutional neural network|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet"/>) or timing after routing directly from the placement information.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer"/>
+[[Place and route#Placement|Placement]] is the task of finding the best spots for large circuit blocks, called macros, and smaller standard cells. Reinforcement learning has been famously used for macro placement, where an agent learns how to position blocks to reduce wire length and improve timing, as shown by Google's research<ref name="Mirhoseini2021Floorplanning"/> and the GoodFloorplan method.<ref name="Xu2021GoodFloorplan"/> Supervised learning models, including [[Convolutional neural network|CNNs]] that treat the layout like a picture, are used to predict routing problems like [[Design rule checking|DRVs]] (e.g., RouteNet<ref name="Xie2018RouteNet"/>) or timing after routing directly from the placement information.<ref name="Rapp2021MLCAD"/><ref name=":0" /> RL Sizer uses deep RL to optimize the size of gates during placement to meet timing goals.<ref name="Lu2021RLSizer"/>
-====Clock Network Synthesis====
+====Clock network synthesis====
 AI helps in Clock Tree Synthesis (CTS) by optimizing the network that distributes the clock signal. GANs, sometimes used with RL (e.g., GAN CTS), are used to predict and improve clock tree structures. The goal is to reduce clock skew and power use.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/><ref name="Chen2024AINativeEDA"/>
 ====Routing====
-[[Place and route#Routing|Routing]] creates the physical wire connections. AI models predict routing traffic jams using methods like GANs to help guide the routing algorithms.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> RL is also used to optimize the order in which wires are routed to reduce errors.<ref name="Rapp2021MLCAD"/>
+[[Place and route#Routing|Routing]] creates the physical wire connections. AI models predict routing traffic jams using methods like GANs to help guide the routing algorithms.<ref name="Rapp2021MLCAD"/><ref name=":0" /> RL is also used to optimize the order in which wires are routed to reduce errors.<ref name="Rapp2021MLCAD"/>
-====Power/Ground Network Synthesis and Analysis====
+====Power/ground network synthesis and analysis====
-AI models, including CNNs and tree based methods, help in designing and analyzing the Power Delivery Network (PDN). They do this by quickly estimating static and dynamic [[IR drop]]. This guides the creation of the PDN and reduces the number of design cycles.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/><ref name="Chen2024AINativeEDA"/>
+AI models, including CNNs and tree based methods, help in designing and analyzing the Power Delivery Network (PDN). They do this by quickly estimating static and dynamic [[IR drop]]. This guides the creation of the PDN and reduces the number of design cycles.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/><ref name=":0" />
-===Verification and Validation===
+===Verification and validation===
-[[Verification and validation (software)|Verification and validation]] are very important to make sure a chip works correctly. AI is used to make these processes, which often take a long time, more efficient.<ref name="Rapp2021MLCAD"/> LLMs are used to turn plain language requirements into formal [[SystemVerilog]] assertions (SVAs) (e.g., AssertLLM)<ref name="Chen2024AINativeEDA"/> and to help with security verification.<ref name="Chen2024AINativeEDA"/> Methods for predicting timing analysis results based on circuit structure, like those first developed by Kahng et al.<ref name="Kahng2018PBAfromGBA"/> and improved with transformer models like TF Predictor,<ref name="Cao2022TFpredictor"/> make the final timing checks much faster. DeepGate2 provides a way to learn circuit representations that understand function, which can help with verification tasks.<ref name="Shi2023DeepGate2"/>
+[[Verification and validation (software)|Verification and validation]] are very important to make sure a chip works correctly. AI is used to make these processes, which often take a long time, more efficient.<ref name="Rapp2021MLCAD"/> LLMs are used to turn plain language requirements into formal [[SystemVerilog]] assertions (SVAs) (e.g., AssertLLM)<ref name=":0" /> and to help with security verification.<ref name=":0" /> Methods for predicting timing analysis results based on circuit structure, like those first developed by Kahng et al.<ref name="Kahng2018PBAfromGBA"/> and improved with transformer models like TF Predictor,<ref name="Cao2022TFpredictor"/> make the final timing checks much faster. DeepGate2 provides a way to learn circuit representations that understand function, which can help with verification tasks.<ref name="Shi2023DeepGate2"/>
-===Analog and Mixed Signal Design===
+===Analog and mixed signal design===
-AI methods are being used more often in the complex field of [[Analog circuit|analog]] and [[Mixed-signal integrated circuit|mixed signal circuit]] design. They are helping to choose the circuit structure, determine the size of components, and automate the layout.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> AI models, including Variational Autoencoders (VAEs) and RL, help to explore and create new circuit structures.<ref name="Chen2024AINativeEDA"/> For instance, graph embeddings can be used to optimize the structure of operational amplifiers.<ref name="Lu2022AnalogTopologyOpt"/> Machine learning substitute models give fast performance estimates for component sizing, while RL directly optimizes the component parameters.<ref name="Chen2024AINativeEDA"/><ref name="Rapp2021MLCAD"/>
+AI methods are being used more often in the complex field of [[Analog circuit|analog]] and [[Mixed-signal integrated circuit|mixed signal circuit]] design. They are helping to choose the circuit structure, determine the size of components, and automate the layout.<ref name="Rapp2021MLCAD"/><ref name=":0" /> AI models, including Variational Autoencoders (VAEs) and RL, help to explore and create new circuit structures.<ref name=":0" /> For instance, graph embeddings can be used to optimize the structure of operational amplifiers.<ref name="Lu2022AnalogTopologyOpt"/> Machine learning substitute models give fast performance estimates for component sizing, while RL directly optimizes the component parameters.<ref name=":0" /><ref name="Rapp2021MLCAD"/>
-===Test, Manufacturing, and Yield Optimization===
+===Test, manufacturing and yield optimization===
 AI helps in the stages after the silicon chip is made, including testing, [[design for manufacturability]] (DFM), and improving the [[Semiconductor device fabrication#Wafer processing|production yield]].<ref name="Rapp2021MLCAD"/> In lithography, AI models like CNNs and GANs are used for SRAF generation (e.g., GAN SRAF<ref name="Alawieh2020GANSRAF"/>) and [[Optical proximity correction|OPC]] (e.g., GAN OPC<ref name="Yang2018GANOPC"/>) to improve how well the chip prints. AI also predicts lithography problems, known as hotspots, from the layout, as shown by Yang et al.<ref name="Yang2017Hotspot"/> For tuning the broader design flow for manufacturing, FIST uses tree based methods to select parameters.<ref name="Xie2020Fist"/>
-===Hardware-Software Co-design===
+===Hardware-software co-design===
 Hardware-Software Co-design is about optimizing the hardware and software parts of a system at the same time. LLMs are starting to be used as tools to help with this. For example, they help in designing Compute in Memory (CiM) DNN accelerators, where how the software is arranged and how the hardware is set up are closely connected, as explored by Yan et al.<ref name="Yan2023LLMsForCiM"/><ref name="Chen2024AINativeEDA"/> LLMs can also create architectural plans (e.g., SpecLLM<ref name="Li2024SpecLLM"/>) or HDL code using benchmarks like VerilogEval<ref name="Liu2023VerilogEval"/> and RTLLM,<ref name="Lu2024RTLLM"/> or with tools like AutoChip.<ref name="Thakur2023AutoChip"/> Additionally, agents based on LLMs like ChatEDA make it easier to interact with EDA tools for different design stages.<ref name="Wu2024ChatEDA"/> For netlist representation, work by Wang et al. focuses on learning embeddings that understand the function of the circuit.<ref name="Wang2022NetlistFunctionality"/>
-==Industry Adoption and Ecosystem==
+==Industry adoption and ecosystem==
 The use of artificial intelligence in electronic design automation is a widespread trend. Many different players in the semiconductor world are helping to create and use these technologies. This includes companies that sell EDA tools and develop software with AI, semiconductor design companies and foundries that use these tools to make and manufacture chips, and very large technology companies that might design their own chips using AI driven methods.
-===EDA Tool Vendors===
+===EDA tool vendors===
 Major EDA companies are leading the way in adding AI to their tool suites to handle growing design complexity. Their strategies often involve creating complete AI platforms. These platforms use machine learning in many different steps of the design and manufacturing process.
-[[Synopsys]] provides a set of tools in its Synopsys.ai initiative. This initiative aims to improve design metrics and productivity from the system architecture stage all the way to manufacturing.<ref name="SynopsysAIBrochure" /> A main component uses reinforcement learning to improve power, performance, and area (PPA) during the process that goes from the initial design description to the final manufacturing file (DSO.ai). Other parts use AI to speed up verification, optimize test pattern generation for manufacturing, and improve the design of analog circuits in different conditions.<ref name="SynopsysAIBrochure" />
+[[Synopsys]] provides a set of tools in its Synopsys.ai initiative. This initiative aims to improve design metrics and productivity from the system architecture stage all the way to manufacturing.<ref name="VirtualGraffitiSynopsysAI" /> A main component uses reinforcement learning to improve power, performance, and area (PPA) during the process that goes from the initial design description to the final manufacturing file (DSO.ai). Other parts use AI to speed up verification, optimize test pattern generation for manufacturing, and improve the design of analog circuits in different conditions.<ref name="VirtualGraffitiSynopsysAI" />
 [[Cadence Design Systems|Cadence]] has created its Cadence.AI platform. The company says it uses "agentic AI workflows" to cut down on the design engineering time for complex SoCs.<ref name="CadenceAIOverview" /> Key platforms use AI to optimize the digital design flow (Cadence Cerebrus), improve verification productivity (Verisium), design custom and analog ICs (Virtuoso Studio), and analyze systems at a high level (Optimality Intelligent System Explorer).<ref name="CadenceAIOverview" /><ref name="CadenceEDAWhatIs" />
@@ Line 113: / Line 116: @@
 [[Siemens|Siemens EDA]] directs its AI strategy at improving its current software engines and workflows to give engineers better design insights.<ref name="SiemensEDAWhitePaper" /> AI is used inside its Calibre platform to speed up manufacturing tasks like Design for Manufacturability (DFM), Resolution Enhancement Techniques (RET), and Optical Proximity Correction (OPC). AI is also used in its Questa suite to close coverage faster in digital verification and in its Solido suite to lessen the characterization work for analog designs.<ref name="SiemensEDAWhitePaper" />
-===Semiconductor Design and FPGA Companies===
+===Semiconductor design and FPGA companies===
 Companies that design semiconductor chips, like FPGAs and adaptive SoCs, are major users and creators of EDA methods that are improved with AI to make their design processes more efficient.
@@ Line 120: / Line 123: @@
 [[Nvidia|NVIDIA]] has a specific Design Automation Research group to look into new EDA methods.<ref name="NVIDIADAResearch" /> The group focuses on EDA tools that are accelerated by GPUs and using AI methods like Bayesian optimization and reinforcement learning for EDA problems. One example of their research is AutoDMP, a tool that automates macro placement using multi objective Bayesian optimization and a GPU accelerated placer.<ref name="NVIDIAAutoDMPBlog" />
-===Cloud Providers and Hyperscalers===
+===Cloud providers and hyperscalers===
 Large cloud service providers and hyperscale companies have two main roles. They provide the powerful and flexible computing power needed to run difficult AI and EDA tasks, and many also design their own custom silicon, often using AI in their internal design processes.
@@ Line 127: / Line 130: @@
 [[IBM]] provides infrastructure on its cloud platform that is focused on EDA, with a strong emphasis on secure environments for foundries and high performance computing.<ref name="IBMEDABlog" /> Their solutions include high performance parallel storage and tools for managing large scale jobs. These are designed to help design houses manage the complex simulation and modeling tasks that are part of modern EDA.<ref name="IBMEDABlog" />
-== Limitations & Challenges ==
+== Limitations and challenges ==
-===Data Quality and Availability===
+===Data quality and availability===
-A main challenge for using AI effectively in EDA is the availability and quality of data.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> Machine learning models, especially deep learning ones, usually need large, varied, and high quality datasets to be trained. This ensures they can work well on new designs they have not seen before.<ref name="Chen2024AINativeEDA"/> However, a lot of the detailed design data in the semiconductor industry is secret and very sensitive. This makes companies unwilling to share it.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> This lack of public, detailed examples makes it difficult for university researchers and for the development of models that can be widely used. Even when data is available, it might have problems like being noisy, incomplete, or unbalanced. For instance, having many more examples of successful designs than ones with problems can lead to biased or poorly performing AI models.<ref name="Gubbi2022Survey"/> The work and cost of collecting, organizing, and correctly labeling large EDA datasets also create big obstacles.<ref name="Chen2024AINativeEDA"/> Solving these data related problems is key for moving AI forward in EDA. Possible solutions include creating strong data augmentation methods, generating realistic synthetic data, and building community platforms for sharing data securely and for benchmarking.<ref name="Chen2024AINativeEDA"/>
+A main challenge for using AI effectively in EDA is the availability and quality of data.<ref name="Rapp2021MLCAD"/><ref name=":0" /> Machine learning models, especially deep learning ones, usually need large, varied, and high quality datasets to be trained. This ensures they can work well on new designs they have not seen before.<ref name=":0" /> However, a lot of the detailed design data in the semiconductor industry is secret and very sensitive. This makes companies unwilling to share it.<ref name="Rapp2021MLCAD"/><ref name=":0" /> This lack of public, detailed examples makes it difficult for university researchers and for the development of models that can be widely used. Even when data is available, it might have problems like being noisy, incomplete, or unbalanced. For instance, having many more examples of successful designs than ones with problems can lead to biased or poorly performing AI models.<ref name="Gubbi2022Survey"/> The work and cost of collecting, organizing, and correctly labeling large EDA datasets also create big obstacles.<ref name=":0" /> Solving these data related problems is key for moving AI forward in EDA. Possible solutions include creating strong data augmentation methods, generating realistic synthetic data, and building community platforms for sharing data securely and for benchmarking.<ref name=":0" />
-===Integration and Compute Cost===
+===Integration and compute cost===
-Putting AI solutions into practice in the EDA field has major challenges. These include fitting the AI into the complex sets of tools that already exist and handling the high cost of computing power.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/> Adding new AI models and algorithms into established EDA workflows, which are often made of many connected tools and private formats, takes a lot of engineering work and can have problems working with other tools.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> Also, training and running complex AI models, especially deep learning ones, requires a lot of computing resources. This includes powerful GPUs or special AI accelerators, large amounts of memory, and long processing times.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> These needs lead to higher costs for both creating and using the AI models.<ref name="Gubbi2022Survey"/> Making AI methods able to handle the ever growing size and complexity of modern chip designs, while staying efficient and using a reasonable amount of memory, is still an ongoing challenge.<ref name="Gubbi2022Survey"/><ref name="Chen2024AINativeEDA"/>
+Putting AI solutions into practice in the EDA field has major challenges. These include fitting the AI into the complex sets of tools that already exist and handling the high cost of computing power.<ref name="Rapp2021MLCAD"/><ref name="Gubbi2022Survey"/> Adding new AI models and algorithms into established EDA workflows, which are often made of many connected tools and private formats, takes a lot of engineering work and can have problems working with other tools.<ref name="Rapp2021MLCAD"/><ref name=":0" /> Also, training and running complex AI models, especially deep learning ones, requires a lot of computing resources. This includes powerful GPUs or special AI accelerators, large amounts of memory, and long processing times.<ref name="Rapp2021MLCAD"/><ref name=":0" /> These needs lead to higher costs for both creating and using the AI models.<ref name="Gubbi2022Survey"/> Making AI methods able to handle the ever growing size and complexity of modern chip designs, while staying efficient and using a reasonable amount of memory, is still an ongoing challenge.<ref name="Gubbi2022Survey"/><ref name=":0" />
-===Intellectual Property and Confidentiality===
+===Intellectual property and confidentiality===
 The use of AI in EDA, especially with sensitive design data, brings up serious worries about protecting secret company information, known as intellectual property (IP), and keeping data private.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> Chip designs are very valuable IP, and there is always a risk when giving this secret information to AI models, particularly if they are made by other companies or run on cloud platforms.<ref name="Rapp2021MLCAD"/> It is extremely important to make sure that design data used for training or making decisions is not compromised, leaked, or used to accidentally leak secret knowledge.<ref name="Chen2024AINativeEDA"/> While strategies like fine tuning open source models on private data are being tried to reduce some privacy risks,<ref name="Chen2024AINativeEDA"/> it is essential to set up secure data handling rules, strong access controls, and clear data management policies. The unwillingness to share detailed design data because of these IP and privacy worries also slows down collaborative research and the creation of better AI models for the EDA industry.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/>
-===Human Oversight and Interpretability===
+===Human oversight and interpretability===
-Even with the push for more automation, the role of human designers is still vital, and making AI models understandable continues to be a challenge.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> Many advanced AI models, especially deep learning systems, can act like "black boxes," which makes it hard for engineers to understand why they make certain predictions or design choices.<ref name="Rapp2021MLCAD"/> This lack of clarity can prevent adoption, as designers might not want to trust or use solutions if their decision making process is not clear, especially in critical applications or when fixing unexpected problems.<ref name="Gubbi2022Survey"/> While AI can automate many jobs, human knowledge is still essential. It is needed to set design goals, check the results from AI, handle new or unusual situations where AI might fail, and provide the specialized knowledge that often guides AI development.<ref name="Rapp2021MLCAD"/><ref name="Chen2024AINativeEDA"/> To effectively use AI in EDA, it means that human engineers and smart tools need to work together effectively. This requires designers to learn new skills for working with and supervising AI systems.<ref name="Chen2024AINativeEDA"/>
+Even with the push for more automation, the role of human designers is still vital, and making AI models understandable continues to be a challenge.<ref name="Rapp2021MLCAD"/><ref name=":0" /> Many advanced AI models, especially deep learning systems, can act like "black boxes," which makes it hard for engineers to understand why they make certain predictions or design choices.<ref name="Rapp2021MLCAD"/> This lack of clarity can prevent adoption, as designers might not want to trust or use solutions if their decision making process is not clear, especially in critical applications or when fixing unexpected problems.<ref name="Gubbi2022Survey"/> While AI can automate many jobs, human knowledge is still essential. It is needed to set design goals, check the results from AI, handle new or unusual situations where AI might fail, and provide the specialized knowledge that often guides AI development.<ref name="Rapp2021MLCAD"/><ref name=":0" /> To effectively use AI in EDA, it means that human engineers and smart tools need to work together effectively. This requires designers to learn new skills for working with and supervising AI systems.<ref name=":0" />
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