Transmeta Efficeon

This is an old revision of this page, as edited by 216.39.22.82 (talk) at 04:34, 13 September 2004. The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

The Transmeta Efficeon processor is their second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip. Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.

Efficeon most closely mirrors the feature set of Intel Pentium 4 processor, although, like AMD Opteron processors, it supports a fully integrated memory controller, a Hypertransport IO bus and supports the NX, or no-execute, AMD64 x86 extension.

Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.