SPARC

SPARC is a RISC microprocessor architecture; it stands for Scalable Processor ARChitecture. It was originally developed in 1985 by Sun Microsystems Inc.; the trademark is now owned by SPARC International, Inc. SPARC CPUs were used, and still are, in the design of various Sun workstations and also to a much lesser extent in the designs from other manufacturers.

History

The SPARC architecture was heavily influenced by the earlier designs of the RISC I & II from the University of California at Berkeley. SPARC was quite minimalist in design (similar to the ARM) and refused any multi-cycle instructions like multiply or divide. It included 128 32-bit integer registers, broken into "windows" of 8. This made subroutine calls inexpensive, instead of having to save out the data from these registers when calling, it simply "moved the window" down and left the original data intact.

The architecture has gone through several revisions, and gained multiply and divide along the way. A number of manufacturers built SPARC based designs, including Texas Instruments and Fujitsu.

A more radical upgrade resulted in the 64-bit UltraSPARC. It added a number of additional units, deeper pipelines, and a series of simple SIMD instructions called VIS.

As of 2002 the current versions are the 32-bit V8 and 64-bit V9.

Features

Some unusual features of the architecture are:

Windowed register file. There are an implemented defined number of registers (expected to be much larger than 32); at any time 24 of these (the register window) are visible as ordinary instruction accessible registers, the window can moved up or down the register file under software control.

The floating point register file can be configured as 32 32-bit registers (single precision) or 16 64-bit registers (double precision) or 8 128-bit registers ("quad precision").

Tagged add and subtract instructions. These perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful if the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

Programming

Like many RISC architectures early versions of the architecture had a branch delay slot which sometimes made coding by hand a little bit awkward. More here obviously.