ARM architecture family
The Acorn RISC Machine (or ARM) is a RISC CPU design that is widely used in a number of applications. It is a very "pure" RISC implementation, and is considered one of the most elegant modern processors.
History
The ARM design was started in 1983 as a project at Acorn, Ltd. After being refused access to the upcoming Intel 80286 for newer generations of their computer line, they responded by starting up a team to design and build a new RISC based CPU, known as the Acorn RISC Machine.
The team, led by Roger Wilson and Steve Furbur, had completed development samples called ARM1 by 1985, and the first "real" production systems as ARM2 the following year. The ARM2 was possibly the simplest real processor in the world, with only 30,000 transistors (compare with the four-year older Motorola 68000's 68000). It featured a 32-bit data bus and 26-bit address bus, with 16 registers and no on-chip cache. This simplicity leads to its excellent low-power needs, and yet it performed better than the 286.
The ARM design team was later spun off from Acorn (itself purchased by Olivetti during the ARM design) and is now a part of Advanced RISC Machines. For this reason you sometimes see ARM lengthened to Advanced RISC Machine instead of Acorn RISC Machine.
The next major milestone was the ARM6 specification, which made the ARM design a true 32-bit CPU, while otherwise remaining similar to earlier models. The latest specification is ARM10, which adds floating point support and 32 registers.
The core has remained largely the same size throughout these changes. ARM2 was 30k transistors, ARM6 grew to only 35k. The idea is that the end-user combines the ARM core with a number of optional parts to produce a complete CPU, one that can be built on old fabs and still deliver lots of performance at a low cost.
DEC licenced the design (which caused some confusion because they also produced the DEC Alpha) and produced the StrongARM. At 233MHz this CPU draws only 1 watt of power. This work was later passed to Intel as a part of a lawsuit settlement, and Intel tookl the opportunity to replace their ailing i960 (and some of the i860) designs with the StrongARM.
Motorola, IBM and Texas Instruments have also licensed the basic ARM design for various uses. The ARM chip has become one of the most used CPU designs in the world, found in everything from hard drives, to mobile phones, to routers.
Design notes
The ARM instruction set follows the 6502 in concept, but includes a number of features designed to allow the CPU to better pipeline them for execution. This includes the addition of a 4-byte condition code on the front of ever instruction, meaning that every instruction can be made a conditional.
This cuts down significantly on the space available for, for example, displacements in memory access instructions, but on the other hand it does make it possible to avoid branch instructions when generating code for small if statements. The standard example of this is Euclid's GCD algorithm:
int
gcd(int i, int j)
{
while (i != j) {
if (i > j)
i -= j;
else
j -= i;
}
return i;
}
Expressed in ARM assembly, the loop, with a little rotation, might look something like
b test
loop subgt Ri,Ri,Rj
suble Rj,Rj,Ri
test cmp Ri,Rj
bne loop
which avoids the branches around the then and else clause that one would typically have to emit.
Another unique feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement "a += (j << 2);" could be rendered as a single instruction on the ARM, register allocation permitting.
This results in the typical ARM program being denser than what would normally be expected of a RISC processor. This implies that there is less need for load/store operations and that the pipeline is being used more effeciently. Even though the ARM runs at what many would consider to be low speeds, it nevertheless competes quite well with much more complex CPU designs.
The ARM processor also has some features rarely seen on other architectures that are considered RISC, such as PC-relative addressing (indeed, on the ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes.
Perhaps in part because of the conditional execution facility using up four bits of every instruction, recent ARM processors have a 16-bit instruction mode, called THUMB. This is intended to allow smaller code where possible.
Another item of note is that the ARM has been around for a while, with the instruction set increasing somewhat over time. Some ARM processors, for example, have no instruction to load a two-byte quantity, so that, strictly speaking, for them it's not possible to generate code that would behave the way one would expect for C objects of type "volatile short".