Intel Core (microarchitecture)

This article is about the new Intel microarchitecture. For Intel processors branded as "Intel Core", such as the 65 nanometre processor codenamed Yonah and its variants, see Intel Core. For the upcoming line of "Intel Core 2" processors using the Intel Core Microarchitecture, see Intel Core 2.

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The Intel Core Microarchitecture is Intel's new processor architecture. It was previously called Intel's Next Generation Microarchitecture before it received its final name. Core-based products will not be branded Pentium. Announced in Q1 2006 the new architecture, developed in Haifa, Israel, to be released later in the year, will replace the old NetBurst and Pentium M microarchitectures.

The architecture features low power usage, multiple cores, Virtualization Technology, EM64T, and SSE4.

The first processors that will use this architecture are code-named Merom, Conroe, and Woodcrest; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest, which is expected to feature the most cores and technologies of all those processors, is for servers.

Intel announced the architecture's official name on March 7, 2006 at the Intel Developer Forum. On May 8, 2006 Intel announced that the Core 2 Duo badge will be used for Conroe and Merom; it has been claimed [1] that the Xeon name will be used for Woodcrest.

Technology

The Intel Core Microarchitecture is designed from the ground up, but similar to the Pentium M in design philosophy. The pipeline is 14 stages — slightly more than Intel Core but less than half of Prescott's, a signature feature of wide order execution cores. Core's execution unit is 4-issues wide, compared to the 3-issue cores of P6, P6-M (Banias and derivatives), and NetBurst microarchitectures. The new architecture is a dual core design with linked L1 cache and shared L2 cache engineered for maximum performance per watt and improved scalability.

One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single microinstruction. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, ramping up speed dynamically as and when needed. This allows the chip to produce less heat, and consume as little power as possible. The front side bus for this new architecture is targeted to run at 1333 MT/s for the Woodcrest, the server and workstation variant, and at 667 MT/s for Merom, the mobile variant, though a second wave of Meroms, supporting an 800 MT/s FSB, is planned. The desktop Conroe version is officially slated to run at 1066 MT/s, with an Extreme Edition at 1333 MT/s, and a budget version at 800 MT/s. Unfortunately, the FSB might prove to be a weak link in the future, as it uses the infrastructure installed in the Pentium 4 era which cannot handle the full peak-bandwidth of dual-channel DDR2 SDRAM, or the new memory architecture FB-DIMM. However, this shouldn't be an immediate problem because of the use of advanced prefetchers and memory-disambiguation which try to hide main-memory-access latency.

Intel says that the power consumption of these new processors is to be extremely low — average use energy consumption is to be in the 1-2 watt range in ultra low voltage variants, with Thermal Design Points (TDPs) of 65 watts for Conroe and 80 watts for Woodcrest. However, this is subject to change. In comparison, an AMD Opteron 875HE processor consumes 55 watts. Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for Ultra Low Voltage (ULV) versions.

Previously, Intel warned that it would focus on power efficiency ("Performance per Watt") rather than raw performance. However, at IDF, Intel advertised both. Some of the promised numbers are:

20% more performance for Merom at the same power level (compared to Core Duo)
40% more performance for Conroe at 40% less power (compared to Pentium D)
80% more performance for Woodcrest at 35% less power (compared to dual-core Xeon)

Road map

Laptops

Merom, first eighth-generation notebook chip, 65 nm, dual-core, 2–4 MiB L2 cache (Release: August 2006)
Penryn, dual-core, 45 nm shrink of Merom, 3–6 MiB L2
Perryville, single-core, 45 nm mobile and desktop processor, 2 MiB L2

Desktops

Conroe, first eighth-generation desktop chip, 65 nm, dual-core, 4 MiB L2 cache (Release: July 23, 2006)
- Allendale, dual-core, cut-down Conroe with 2 MiB L2
  - Millville, single-core, cut-down Allendale with 1 MiB L2
  - Wolfdale, dual-core, 45 nm shrink of Allendale, with 3 MiB L2
- Kentsfield, quad-core MCM, consists of two Conroes, with 2 × 4 MiB L2 (8 MiB L2)
  - Yorkfield, eight-core MCM, 45 nm, 12 MiB L2, successor to Kentsfield
- Ridgefield, dual-core, 45 nm shrink of Conroe, with 6 MiB L2
Perryville, single-core, 45 nm mobile and desktop processor, 2 MiB L2

Servers and workstations

Woodcrest, first eighth-generation server and workstation chip, 65 nm, dual-core, 4 MiB L2 cache (Release: June 19, 2006)
Clovertown, quad-core MCM, consists of two Woodcrests, with 2 × 4 MiB L2
Clovertown-MP, MP-capable version of Clovertown
Tigerton, quad-core, MP-capable. Based on Tulsa processor, that is quad-core with two Woodcrest Cores.
Harpertown, either a dual-core, 45 nm shrink of Woodcrest, or an eight-core, 45 nm MCM with 12 MiB L2
Dunnington, four to thirty-two cores, successor to Tigerton

References