Jump to content

ICL Distributed Array Processor

Edit links
From Wikipedia, the free encyclopedia

The Distributed Array Processor (DAP) produced by International Computers Limited (ICL) was the world's first commercial massively parallel computer. The original paper study was complete in 1972 and building of the prototype began in 1974. The first machine was delivered to Queen Mary College in 1979.[1]

Development

[edit]

The initial Pilot DAP was designed and implemented by Dr Stewart F Reddaway with the aid of David J Hunt and Peter M Flanders at the ICL Stevenage Labs.[citation needed] Their manager and a major contributor was John K Iliffe, designer of the Basic Language Machine and known for Iliffe vectors.[2] The pilot implementation had a 32×32 processing element arrangement.[3]

The ICL DAP had 64×64 single bit processing elements (PEs) with 4096 bits of storage per PE. It was attached to an ICL mainframe and its memory was mapped into the mainframe's memory. Programs for the DAP were written in DAP FORTRAN which was FORTRAN extended with 64×64 matrix and 64 element vector primitives. DAP Fortran compiled to an assembly language called APAL (Array Processor Assembly Language). The DAP had a single instruction, multiple data (SIMD) architecture. Each operation could be performed under the control of a mask which controlled which elements were affected. Array programs were executed as subroutines of normal mainframe FORTRAN programs and IO was handled by the mainframe.

Operationally, there was an overhead to transfer computational data into and out of the array, and problems which did not fit the 64×64 matrix imposed additional complexity to handle the boundaries (65×65 was perhaps the worst case!)—but for problems which suited the architecture, it could outperform the current Cray pipeline architectures by two orders of magnitude. The ICL 2980 was not a popular machine and this held back the use of the DAP as an attached processor was restricted initially to this one range.

The design as described in Reddaway's 1973 paper is pretty much that which was implemented in the first commercial version except the facility to supply address bits from the processing elements was removed. This change greatly simplified hardware error detection. A notable extra facility was carry propagation to simplify vector mode addition.[4]

After ICL

[edit]

The DAP [IP] was sold off to a venture capital-funded start-up company Active Memory Technology (AMT) which was then taken over by Cambridge Parallel Processors (CPP). It was enhanced and made smaller and faster as the Gamma series. An 8-bit processor with some local 8-bit wide memory was added to the processor and fast IO capabilities were implemented. It could be programmed in either C++ or Fortran-Plus. These were more flexible than DAP FORTRAN, in particular they automatically took care of choosing a mapping from user specified matrix and vector bounds to the underlying hardware.

Sample DAPs are in storage at the Computer History Museum.

CPP ceased trading in 2004.

Mini-DAP and Mil-DAP

[edit]

Between 1984 and 1987, ICL developed a scaled-down version of the original DAP featuring a 32×32 array of processing elements. The commercial iteration was marketed as the Mini-DAP and was typically interfaced to the PERQ workstation, earning it the alternative name PERQ-DAP.[5]

ICL's Research Applications Laboratory (RAL) recognized the Mini-DAP as a "very fast add-on parallel processor to the ICL PERQ", particularly effective for image-processing workloads where the DAP’s memory could serve as a bitmap frame buffer.[5] Initial prototype work began around mid-1983, with delivery to RAL delayed from early 1985 due to interface development challenges.[5]

A military-grade version, dubbed the Mil-DAP, was also created. This ruggedized variant was designed to withstand field deployment and environmental extremes. One surviving specimen, serial number M002/005, is identified as an early example of parallel processor computers in military use.[6][7]

See also

[edit]

References

[edit]
  1. ^ Gordon G Scarrott (Summer 1995). "From Torsional Mode Delay Lines to DAP". Computer Resurrection (12).
  2. ^ Stewart Reddaway (Spring 2004). "Letter to the editor". Computer Resurrection. 48 (33): 149–150. doi:10.1016/j.lungcan.2004.09.011. PMID 15777984.
  3. ^ Parkinson, Dennis (17 June 1976). "Computers by the thousand". New Scientist. pp. 626–627. Retrieved 7 July 2024.
  4. ^ S. F. Reddaway (1973). "DAP—a distributed array processor" (PDF). ACM SIGARCH Computer Architecture News. 2 (4). ACM Press: 61–65. doi:10.1145/633642.803971.
  5. ^ a b c "DAP 510 Brochures". Chilton Computing / UKRI Science and Technology Facilities Council. Retrieved 25 June 2025.
  6. ^ "Parallel Processor Computer – Mil-DAP". Science Museum Group Collection. Retrieved 25 June 2025.
  7. ^ "MIL-DAP parallel processor computer, c.1979". Getty Images. Retrieved 25 June 2025.
[edit]
Retrieved from "https://en.wikipedia.org/w/index.php?title=ICL_Distributed_Array_Processor&oldid=1297323488"