Intel QuickPath Interconnect
The Intel QuickPath Interconnect ("QuickPath", "QPI")[1][2][3] is a point-to-point processor interconnect developed by Intel to compete with HyperTransport. Prior to the announcement of the name, Intel referred to it as Common System Interface or "CSI". Earlier incarnations were known as YAP (Yet Another Protocol) and YAP+. The development was conducted at Intel's MMDC (Massachusetts Microprocessor Design Center) by members of DEC's Alpha Development Group (acquired by Intel). It will replace the Front Side Bus (FSB) for Desktop, Xeon, and Itanium platforms. Intel first delivered it in November 2008 on the Intel Core i7 desktop processor and the X58 chipset, and it will be used on new Nehalem-based Xeon processors[4] and Tukwila-based Itanium processors.[5]
The QPI is an element of a system architecture that Intel calls the QuickPath architecture that implements what Intel calls QuickPath technology.[6] In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub (e.g., to connect a Core i7 to an X58.) In more complex instances of the architecture, separate QPI links connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with AMD's Hypertransport, the QuickPath Architecture assumes that the processors will have integrated memory controllers, so a multiprocessor system implements a NUMA architecture.
Each QPI comprises two 20-bit point-to-point links, one in each direction, with a separate clock in each direction, for a total of 42 signals. Each signal is a differential pair, so the total number of pins is 84.
Performance numbers for QuickPath are reported to be 4.8 to 6.4 Gigatransfers per second (GT/s) per direction. Therefore the bandwidth amounts to 12.0 to 16.0 GB/s per direction, or 24.0 to 32.0 GB/s per link.[7]
On high-reliability servers, A QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 15+1, 10+1, or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails.
The initial Nehalem implementation uses a 20-bit wide 25.6 GB/s link (as reported in the Intel Nehalem Speech on IDF). This 25.6 GB/s link provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset.
See also
References
- ^ Intel® QuickPath Technology: Intel's Overview & Video Preview, retrieved October 19, 2008
- ^ The Inquirer: Intel CSI name revealed, retrieved May 16, 2007
- ^ DailyTech report, retrieved August 21, 2007
- ^ VR-Zone report, retrieved July 17, 2007
- ^ "Intel's Tukwila Confirmed to be Quad Core". 5 May 2006.
- ^ "Intel Demonstrates Industry's First 32nm Chip and Next-Generation Nehalem Microprocessor Architecture". Retrieved 2007-12-31.
- ^ Realworld Technologies report, retrieved August 28, 2007
- The Inquirer: Intel gets knickers in a twist over Tanglewood
- The Inquirer: Intel's Whitefield takes four core IA-32 shape
- CRN: Intel preps HyperTransport competitor for Xeon, Itanium CPUs
- The Register: Intel's CSI to outperform AMD's Hypertransport
- Real World Tech: Intel Tukwila confirmed to be Quad-core
- ZDNet Asia: Intel server revamp to follow AMD
External links
- Nehalem News
- First Look at Nehalem Microarchitecture
- Ars Technica's What You Need To Know About Nehalem
- Everything You Need to Know About The QuickPath Interconnect (QPI)
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