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A typical large ND-500 configuration.

The ND-500 was a 32-bit superminicomputer delivered in 1981 by Norsk Data priced from £75,000 for the base model. It relied on a ND-100 to do housekeeping tasks and run the OS, SINTRAN III.[1] A configuration could feature up to four ND-500 CPUs in a shared-memory configuration.

System architecture

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The ND-500 combined a 32-bit system based on one or more Nord-500 or ND-500 processors with a ND-100 minicomputer responsible for input/output handling, job scheduling, management of the ND-500 system, and providing a multi-user environment based on the SINTRAN III/VS operating system. This arrangement largely preserved the general architecture of systems based on the preceding Nord-5 and Nord-50 models, and in keeping with those models, the 32-bit component of the ND-500 was aimed at "simulation, numerical analysis and scientific" workloads.[2]

The ND-500 processor employed split data and instruction caches, running with a 110 nanosecond cycle time, along with similarly separated memory management units, thus permitting access to a full 32-bit address space for both program instructions and data. A total 32 MB of physical memory was supported. Physical memory was shared between the ND-100 and ND-500 systems, exposed in a "multiport" arrangement, with the ND-500 having two paths to this RAM, the ND-100 having one path, and the direct memory access hardware having its own path. A prefetch processor was used to decode instructions fetched from memory, to populate the execution pipeline, and to initiate memory accesses for referenced addresses. This processor operated concurrently with the arithmetic logic unit.[2]

Processor architecture

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The instruction set of the ND-500, featuring "184 basic instruction codes" specialised by several data types and addressing modes, along with "few and specialized" registers, lent itself to an instruction encoding of only one or two bytes, albeit with the potential for several accompanying operands, up to 256 in number.[3] Operands could be from one to nine bytes in length, and thus the documentation for the ND-500 notes, "The shortest instructions are one byte long, the longest may be several thousand bytes long."[4]: 117  This contrasted strongly with the design of the CPU in its predecessor, the Nord-50, which featured 32-bit instructions in only three formats and the availability of 64 general-purpose registers.[5]

The ND-500 processor provides only four 32-bit registers for use as integer accumulators or index registers, I1 through I4, and four 32-bit registers for use as floating-point accumulators, A1 through A4, each extended by one of four extension registers, E1 through E4, to provide 64-bit registers for double-precision floating-point operations. Base registers B and R provide access to local variables and record storage respectively. Several other special-purpose registers are provided such as the program counter (P), link or subroutine return address (L), top-of-stack (TOS), plus registers related to trap handling, processor status, and process characteristics. Of the 50 documented registers in the ND-500, several are reserved for use by the processor's microprogram.[4]

Thus, in its selection of registers, the ND-500 processor more strongly resembles the ND-100 which, at each priority level, provides a single accumulator (A), index register (X), base register (B), extension register (D), program counter (P), link register (L), along with a temporary register (T) mostly used for floating-point operations, and a status register (STS). Unlike the ND-500, the ND-100 preserves the fixed-size, 16-bit instruction format of the earlier Nord-10 series, but like the ND-500, the ND-100 processor is microprogrammed.[6]: 2–1, 2–6, 3–1 

Promotional materials for the ND-500 emphasised the "highly symmetric" or orthogonal instruction set, permitting the use of all addressing modes with all instruction types and with all data types, providing memory-to-memory instructions able to retrieve operands, perform computational operations, and store results. Such materials claimed a higher code density than most 16-bit computers despite the 32-bit nature of the ND-500 processor.[7]: 5 

The cache architecture of the ND-500 employed virtual addresses instead of physical addresses to allow cache lookup and address translation to occur in parallel,[3] a strategy also employed by the PA-RISC architecture.[8]: 32  The ND-500 architecture employed a "write-through" cache strategy, but a small, high-speed write buffer allowed the processor to proceed while the cache controller populated the cache and issued writes to memory.[7]: 113, 116 

The ND-5000 cache implementation differed from that of the ND-500,[4]: 47  employing a "write-once" strategy that issued a memory write when first recording data to be stored in the cache for a particular location. Such an approach aimed to achieve the efficiency of a write-back strategy by largely avoiding main memory access. However, a write-back strategy with the virtually addressed cache was regarded as presenting difficulties should a write-back to memory occur at a later point in time and cause a page fault. The write-once approach avoided such complications by establishing an initial memory mapping and reserving it for eventual writes to memory. A write-through strategy could also be selected through a processor configuration register.[9]: 52–54 

Hardware implementations

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In its first incarnation, the ND-500 was built using TTL integrated circuits, just as the Nord-50 had been.[3] The floating-point processor featured in the ND-500 reportedly consisted of 579 integrated circuits and used a combinatorial approach to support the execution of 64-bit multiplication operations in 480 nanoseconds.[10] Norsk Data claimed a Whetstone benchmark rating of 1.4 to 1.8 million single-precision Whetstone instructions per second for the ND-500.[3]

The ND-500 architecture lived through four distinct implementations. Each implementation was sold under a variety of different model numbers.

ND also sold multiprocessor configurations, naming them ND-580/n and an ND-590n, where n represented the number of CPUs in a given configuration, 2, 3, or 4.

ND-500/1

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Sold as the ND-500, ND-520, ND-540, and ND-560.

ND-500/2

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Sold as the ND-570, ND-570/CX, and ND-570/ACX.

The ND-500/CX series upgraded the ND-500 range during 1984, introducing the ND-530/CX, ND-550/CX, ND-560/CX and ND-570/CX in a range of different product variants, including the compact model III for the lower-end products. Advertised performance figures were given as 0.6, 1.3, 2.1 and 3.3 million Whetstone instructions per second for the respective products.[11]

ND-505

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The ND-505[12] was a version of the ND-500 machine with 29 bit addressing space. Pins were essentially snipped on the backplane, removing its status as a superminicomputer, allowing it to legally pass the CoCom embargo in force at the time and be exported to the Eastern Bloc.

Samson

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Sold as the ND-5200, ND-5400, ND-5500, ND-5700, ND-5800 and ND-5900. The ND-120 CPU line, which constituted the ND-100 side of the three higher-end ND-5000 computers, was named Delilah. The ND-110 accompanied the three lower-end models.[9] As the 500/5000 line progressed in speed, the dual-arch ND-100/500 configuration increasingly became bottlenecked by all input/output (I/O) having to go through the ND-100.[13]: 10 

The ND-5700, ND-5800 and ND-5900 were introduced in 1987 as high-end models, employing "state-of-the-art CMOS gate array technology" to reduce the footprint of the CPU implementation, replacing the 24 circuit boards required in the previous ND-500 architecture models. The ND-5900 was a multi-CPU model featuring two, three or four CPUs. Performance varied between the models, with the ND-5700 delivering half the performance of the ND-5800, and with the ND-5900 models respectively delivering two, three and four times the performance of the ND-5800.[14] Pricing for the models started at $400,000 for the ND-5700, reaching $1.53 million for the four-CPU ND-5900.[15]

Later models were introduced at the low end of the range in the form of the ND-5000 Compact series, aimed at small and medium-size companies and featuring a cabinet size with "modest dimensions", "occupying less than a square metre of floor space", and designed for a conventional office environment, as opposed to a dedicated machine room. Offered as the ND-5200 Compact, ND-5400 Compact, ND-5500 Compact and ND-5700 Compact, supporting smaller amounts of memory than the earlier ND-5000 models, performance of the high-end ND-5700 Compact was around that of the conventional ND-5700 model.[16]

The Compact series generally offered a reported 0.5 to 3.5 million Whetstone instructions per second across the different models. Norsk Data claimed that this was "the world's largest compatible range" of computers, or perhaps the industry's range with broadest performance characteristics across compatible models, with the top-end ND-5900 Model 4 delivering a claimed 26 million Whetstone instructions per second.[16][17][note 1]

The ND-5900/4 featured in Norsk Data's proposal for the FUNN regional research and development network programme, initiated in 1987 after a proposal was made to the Norwegian government to establish publicly-funded regional computing centres.[18]: 3  Described as Norsk Data's largest and newest machine, each unit of the specified configuration would be delivered running SINTRAN III and NDIX, the latter to satisify a requirement for availability of a "standardised UNIX" for software portability and to minimise vendor lock-in,[18]: 6  with these operating systems running in parallel on the hardware.[18]: 14  The cost of each installed machine was almost 13 million NOK, equivalent to $1.51 million, and approximately 27 million NOK or $3.14 million today.[18]: 9  The FUNN initiative itself was described as one of the last attempts to rescue Norsk Data, "a complete fiasco project leading to nothing", partly due to the delivered systems lacking relevant software and the necessary interoperability for a genuine multi-vendor solution.[19]

Rallar

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Sold as the ND-5830 and ND-5850. The Rallar processor consisted of two main VLSI gate arrays, KUSK (En: Jockey) and GAMP (En: Horse).[citation needed]

In 1988, with the introduction of Norsk Data's Extended System Architecture, this being the company's open systems strategy, two models of the ND-5000 ES (Extended Server) product were unveiled: the low-end Model S as an "affordable supermini in micro format", and the more powerful Model C as a departmental server based on the ND-5800 SE processor, yielding an almost two-fold performance improvement over earlier products.[20]

Alongside these newer ND-5000-based models, the company also introduced the ND-5100/xi system. Despite adherence to the existing naming convention, this was actually a system based on the Intel 80386 running SCO Xenix System V, offered in 14 different configurations.[20] This inconsistent branding persisted with the incorporation of the ND-5000 technology into Norsk Data's Uniline range, consisting of three models based on the Intel 80386 having the Uniline 10, 20 and 40 designations, alongside the Uniline 35, 45 and 55 models based on the ND-5000.[21]: 6 

From 1990, upgrades were offered for ND-5000 models having the Uniline or ND-5000 ES designation to deliver an upgraded system with Uniline 88/20C specifications, thus becoming a system based on the Motorola 88000 architecture running a Unix implementation provided by UniSoft. Apart from the low-end Uniline 88/17Jr model based on the Data General Aviion 3200 which ran DG/UX, the Uniline 88 range was developed by the Norsk Data spin-off, Dolphin Server Technology.[22]: 54, 56, 59, 62 

Software

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LED was a programmer's source-code editor by Norsk Data running on the ND-500 computers running Sintran III. It featured automatic indenting, pretty-printing of source code, and integration with the compiler environment. It was sold as an advanced alternative to PED. Several copies exist, and it is installed on the NODAF public access ND-5700.

In 1984, Norsk Data contracted Logica to undertake a project to port Berkeley Software Distribution (BSD) 4.2 Unix to the ND-500/CX, this being described as Logica's first attempt to port BSD 4.2 despite "extensive experience with Microsoft's Xenix".[23] The purpose of this effort was so that ND could sell the 500 to the European Organization for Nuclear Research (CERN), since CERN along with other technical and scientific users had been buying VAXes from Digital Equipment Corporation, and CERN's accelerators and experiments had begun to standardise on multi-vendor technologies such as Unix. Initial deliveries of the work were made to CERN during the 1986 financial year.[24] A C compiler from Luleå University College in Northern Sweden was used. The goal was to port Unix BSD to the ND-500 and use the ND-100 running Sintran-III as the front end. Thus, all I/O had to go through the ND-100 which proved very inefficient. For example, running vi on the ND-500 brought the ND-100 to its knees.[citation needed]

The ND-500 struggled to meet CERN's goals as a Unix system, with the Unix implementation, NDIX, described as "not being entirely satisfactory" after more than two years of slow progress on the implementation.[25] More enthusiastic commentary acknowledged the ND-500's "problems with I/O performance" under NDIX, along with fundamental architectural limitations of ND-500 systems, but claimed that "now (on a ND-570) it is generally better than a VAX-785 whilst its processing performance is far superior".[note 2] Nevertheless, further adoption of Norsk Data machines was noted as being contingent on the company recognising the architectural limitations of the ND-500 and continuing to collaborate with CERN on enhancements. Norsk Data was, however, perceived as favouring its own proprietary operating system over NDIX.[13]

With the launch of the ND-5000 Compact models in 1987, Norsk Data promised the later availability of a POSIX-compliant Unix system running concurrently with Sintran on the main ND-5000 processor, as opposed to running within Sintran, persisting with the use of Sintran on the front-end ND-100 series processor.[26]

Reception

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Fundamentally, despite a claimed performance advantage of 60–70% over a VAX system, the ND-500 could not compete with the superior VAX I/O architecture, initially supporting only a single user at a time using ND's own software environment, stretching to up to five concurrent users under pressure from customers. Only eventually could some ND-500 installations support up to 40 concurrent users.[27]: 99–100  Given the established usage of Norsk Data computers at CERN, some adoption of the ND-500 did occur, such as in the organisation's PS division where a ND-570 model was used for program development and use of the ND-NOTIS suite.[28]

However, by 1987, VAX systems had emerged as a "de facto" standard in particle physics experiments, having been adopted by CERN's LEP collaborations, leaving opportunities for Norsk Data largely confined to "extensions, upgrades and replacements" within various existing control systems.[29] By 1989, CERN's experiments were using over 100 VAX and MicroVAX computers, and of the 20 or more Norsk Data computers in use, six were ND-500 series models. The organisation's accelerator divisions employed around 110 ND-100 series models, with the PS and SPS divisions each having two ND-570 systems. However, about 100 IBM PC/AT systems were also being used, alongside an increasing number of workstations. Across the whole of CERN, over 120 Apollo workstations and over 250 VAXstations had been taken into use.[30]

By 1990, it had become apparent that the ND-100 series machines still in use in CERN's SPS control system, numbering over 50 units, were faced with "technical obsolescence" and prohibitive maintenance costs.[31] Their proprietary operating system and network technology inhibited the use of "modern software packages and communication standards", leading to a "necessary and urgent" need to consolidate the affected control systems with those of the LEP,[32] the LEP control system architecture being largely based on personal computers running Xenix and workstations running Unix.[33] Ultimately, the ND-100 series machines were replaced with a combination of Unix systems and X terminals for control room functionality and systems running LynxOS for process control functionality. Despite the removal of the Norsk Data systems, facilities were developed and retained to execute programs written in NODAL in an emulated environment, thus preserving "the enormous investment in application programs" and corresponding programming environment, and allowing the control console user interface to be replicated in the new environment within a reasonable timeframe.[34] NODAL was an interpreted language "based on FOCAL and SNOBOL4, with influence from BASIC".[35]

ND-5000 models incorporated the Motorola 68020 as input/output controllers,[26] and an interfacing concept known as DOMINO was able to provide the ND-5000 range with VMEbus connectivity. This enabled interoperability with existing hardware architectures used in domains such as particle physics.[36] Utilisation of the "powerful 68020 processor" gave the ND-5000's system bus a bandwidth of 18 MB per second and enabled its use as a front-end system for the CESAR systolic array processor, designed to process synthetic aperture radar data.[37] The control processor for the CESAR system had previously employed the Motorola 68000, with a ND-100 minicomputer acting as the host computer or front-end system.[38] Due to the system architecture of the ND-5000, the later CESAR system architecture also featured a ND-120 minicomputer acting as the input/output front-end for lower-performance devices.[37]

References

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  1. ^ Cahill, Kevin (9 April 1981). "Norsk launches first European 32-bit mini". Computer Weekly. p. 3. Retrieved 24 June 2024.
  2. ^ a b "16- and 32-Bit Computers Adapt Readily to Changing Requirements". Computer Design. September 1979. pp. 64–65. Retrieved 30 June 2024.
  3. ^ a b c d Knudsen, Per (11 August 1982). "Supermini goes multiprocessor route to put it up front in performance" (PDF). Electronics. pp. 112–117. Retrieved 1 July 2024.
  4. ^ a b c ND-500 Reference Manual (PDF). Norsk Data AS. June 1987. Retrieved 28 August 2024.
  5. ^ NORD-50 Reference Manual (PDF). Norsk Data AS. February 1976. Retrieved 26 August 2024.
  6. ^ ND-100 Reference Manual (PDF). Norsk Data AS. January 1982. Retrieved 4 September 2024.
  7. ^ a b ND-500 Central Processing Unit (PDF). Norsk Data AS. April 1981. Retrieved 7 September 2024.
  8. ^ Chao, Chia; Mackey, Milon; Sears, Bart (4–5 October 1990). "Mach on a virtually addressed cache architecture". Mach Workshop Proceedings. Burlington, Vermont: USENIX Association. pp. 31–51.
  9. ^ a b ND-5000 Hardware Description (PDF). Norsk Data. April 1988. p. 4. Retrieved 25 May 2025.
  10. ^ Waser, Shlomo; Flynn, Michael J. (1982). Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing. p. 211. ISBN 0-03-060571-7. Retrieved 30 June 2024.
  11. ^ "The ND-500/CX Series – a new profile for high-end systems" (PDF). ND News. November 1984. p. 30. Retrieved 6 July 2024.
  12. ^ "ND 505/CX COMPUTER SYSTEM" (PDF). Norsk Data. Retrieved 25 November 2024.
  13. ^ a b Crutcher, A. (12 November 1986). The Mysterious 500 (PDF) (Technical report). CERN. Retrieved 19 May 2025.
  14. ^ Bakke, Henrik; Moini, Zaira (March 1987). "The ND-5000 Series: Removing Hardware Limitations" (PDF). ND News. pp. 52–53. Retrieved 6 July 2024.
  15. ^ Connolly, James (23 February 1987). "Norsk adds high-end system to ND-5000 series". Computerworld. p. 48. Retrieved 9 July 2024.
  16. ^ a b Hasting, Arvid (September 1987). "Powerful Computers Now also for Smaller Companies" (PDF). ND News. pp. 70–71. Retrieved 6 July 2024.
  17. ^ Annual Report 1986 (PDF). Norsk Data. May 1987. p. 34. Retrieved 7 July 2024.
  18. ^ a b c d Oppbygging av IT-kompetansesentra i Distrikts-Norge (in Norwegian). Norges Teknisk-Naturvitenskapelige Forskningsråd. December 1987. Retrieved 24 April 2025.
  19. ^ Haraldsen, Arild (2005). 50 år – og bare begynnelsen (in Norwegian). Cappellen Akademisk Forlag. pp. 105–106. ISBN 82-02-22616-3. Retrieved 24 April 2025.
  20. ^ a b Jensen, Jan Roald (October 1988). "Product announcements" (PDF). ND News. pp. 40–42. Retrieved 6 July 2024.
  21. ^ Uniline: En komplett UNIX-løsning fra Norsk Data (PDF) (in Norwegian). Norsk Data AS. May 1989. Retrieved 8 September 2024.
  22. ^ Price Catalogue Autumn 1990 (PDF). Norsk Data AS. October 1990. Retrieved 8 September 2024.
  23. ^ "News in brief" (PDF). ND News. November 1984. p. 33. Retrieved 6 July 2024.
  24. ^ Annual Review 1986 (PDF). Logica plc. 24 September 1986. p. 28. Retrieved 19 May 2025.
  25. ^ Crowley-Milling, M. C. (October 1987). The Evolution of the Control System for the LEP (PDF) (Technical report). CERN. p. 30. Retrieved 19 May 2025.
  26. ^ a b "Norsk Data Promises Posix, Fleshes out ND5000 Mini Line". Unigram/X. 22 August 1987. p. 3.
  27. ^ Steine, Tor Olav (1992). Fenomenet Norsk Data (in Norwegian). Oslo: Universitetsforlaget. ISBN 82-00-21501-6.
  28. ^ Shering, George (30 September 1986). Notis on the PS Controls Computer (PDF) (Technical report). Retrieved 30 April 2025.
  29. ^ Proposal to renew, without competive tenderingm two existing contracts covering the purchase of computing equipment for the CERN accelerator control systems and experimental requirements (Report). 18 February 1987. Retrieved 30 April 2025.
  30. ^ Allaby, J.; Billinge, R.; Bock, R.; Bunn, J.; Dydak, F.; Ericson, T.; Ferguson, J.; Jacobs, D.; Jones, C.; Sacton, J.; Thresher, J.; Williams, D. (14 July 1989). Computing at CERN in the 1990s – The Report of the Steering Committee (Report). CERN. p. 46. Retrieved 21 May 2025.
  31. ^ Controls Users Meeting at Chamonix (Technical report). CERN. 17 July 1990. p. 7. Retrieved 17 May 2025.
  32. ^ PS/SL controls consolidation project (Technical report). CERN. April 1991. p. 8. Retrieved 17 May 2025.
  33. ^ Innocenti, P. G. (October 1989). The LEP Control System. International Conference on Accelerator and Large Experimental Physics Control Systems. p. 7. Retrieved 17 May 2025.
  34. ^ Charrue, P.; Clayton, M. J. (28 November 1995). The New Controls Infrastructure for the SPS (Technical report). CERN. Retrieved 17 May 2025.
  35. ^ Crowley-Milling, Michael C.; Shering, George C. (1978). The NODAL system for the SPS (Technical report). CERN. p. 1. Retrieved 22 May 2025.
  36. ^ Ramsøy, Tore (1991). DAISY. University of Oslo, Department of Physics. ISSN 0332-5571. Retrieved 26 April 2025.
  37. ^ a b Måøy, Arve; Holm, Sverre; Toverud, Morten (March 1990). "Design of a Processing Facility for Synthetic Aperture Radar Data at the Tromsø ERS-1 Ground Station". Journal of the British Interplanetary Society. 43: 94–100. Retrieved 4 May 2025.
  38. ^ Andersen, Vidar S; Haugland, Torstein; Søråsen, Oddvar (16–20 December 1985). CESAR – A Programmable Systolic Array Multiprocessor System. First International Conference on Supercomputing Systems. IEEE Computer Society Press. pp. 8–15. ISBN 0-8186-0654-1. Retrieved 4 May 2025.

Notes

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  1. ^ Note that Norsk Data uses the term "Mips" in its description of the Compact series, not explicitly referencing any industry-defined performance metric, leaving such figures open to interpretation. However, the 1986 annual report, published in 1987, indicates "26 Whetstone MIPS" for the cumulative performance rating of the four-CPU model.
  2. ^ Independent measurements put the VAX-11/785 at around 1.65 MWIPS against a claimed 3.3 MWIPS for the ND-570/CX.
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