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29 June 2025
- diffhist Central processing unit 15:08 +255 14.151.17.224 talk (→Microprocessors)
28 June 2025
- diffhist Complex instruction set computer 22:17 +291 Ylee talk contribs (→CISC and RISC terms: Intel did improve x86)
- diffhist Complex instruction set computer 20:19 +12 Guy Harris talk contribs (→CISC and RISC terms: For x86 and 68k, go with the series, not just particular processors. (PDP-10 and PDP-8 refer to series, as do IBM Z (updated from System z) and VAX.)
- diffhist Complex instruction set computer 20:16 +11 Guy Harris talk contribs (→CISC and RISC terms: Sun only briefly used the 68000; they switched to the 68010 as soon as possible, so that they could support 4.2BSD demand paging without Apollo-style dual-processor tricks, and then switched to the 68020 and finally 68030.)
- diffhist Complex instruction set computer 20:12 −37 Guy Harris talk contribs (→CISC and RISC terms: {{citation needed}} and {{failed verification}} do not go together - {{failed verification}} means that the source doesn't support the claim, so at least there's a source; {{citation needed}} means there isn't a source.)
- diffhist Complex instruction set computer 20:10 −11 Guy Harris talk contribs (→CISC and RISC terms: Also chosen by NexGen and AMD for x86, so just say "and x86".)
- diffhist Complex instruction set computer 19:23 +884 Ylee talk contribs (→CISC and RISC terms: CISC's response to RISC)
- diffhist m East Fishkill, New York 07:07 +40 Panamitsu talk contribs (add {{Use American English}} template per MOS:TIES) Tag: AWB
27 June 2025
- diffhist m Instruction set architecture 19:12 −31 LightlySeared talk contribs (Reverted 1 edit by 78.149.38.121 (talk) to last revision by RastaKins) Tags: Twinkle Undo
- diffhist Instruction set architecture 19:12 +31 78.149.38.121 talk Tag: Reverted
- diffhist PL/I 00:23 −21 Guy Harris talk contribs (→Early history: The IEEE reference doesn't mention PL/I CHARACTER. This UNC at Chapel Hill obituary does.)
26 June 2025
- diffhist m Encryption 08:51 +388 Meters talk contribs (Reverted edit by 2806:2A0:91E:8F42:1B1A:FE99:3BB8:515D (talk) to last version by MrOllie) Tag: Rollback
- diffhist Encryption 08:36 −388 2806:2a0:91e:8f42:1b1a:fe99:3bb8:515d talk Tags: Reverted Visual edit Mobile edit Mobile web edit
25 June 2025
- diffhist m CPU cache 00:25 0 GreenDevolution talk contribs (Minor fix to make use of higher/lower level consistent) Tag: Visual edit
24 June 2025
- diffhist CPU cache 14:57 +66 GreenDevolution talk contribs (Make usage of higher/lower cache levels consistent. Hennessy and Patterson describe L1 cache as the highest-level cache.) Tag: Visual edit
23 June 2025
- diffhist PowerPC 600 18:40 +526 113.157.217.50 talk (Changes to reflect the bus lineage of the 6XX and POWER4 designs. I can't find any reference to the 'snake' chips. The variate with Orca was called Race/Whip to bridge 6xx , DRAM, and MX. MX to PCI was the Python chip.)
- diffhist Central processing unit 15:47 +68 Fgnievinski talk contribs (→Privileged modes)