Static random-access memory
Static random access memory (SRAM) is a type of semiconductor memory. The word "static" indicates that the memory retains its contents as long as power remains applied, unlike dynamic RAM (DRAM) that needs to be periodically refreshed. (Nevertheless, SRAM should not be confused with read-only memory and flash memory, since it is volatile memory and preserves data only while power is continuously applied.) SRAM should not be confused with SDRAM, which stands for synchronous DRAM and is entirely different from SRAM, or with pseudostatic RAM (PSRAM), which is DRAM disguised as SRAM.
Design
Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. It thus typically takes six MOSFETs to store one memory bit.
Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to be bit lines: BL and BL. They are used to transfer data for both read and write operations. While it's not strictly necessary to have two bit lines both the signal and its inverse are typically provided since it improves noise margins.
The symmetric circuit structure allows the value of a memory location to be read much faster than in a DRAM. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. As opposed to this, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.
The size of an SRAM with m address lines and n data lines is words, or bits.
SRAM operation
A SRAM cell has three different states it can be in: standby where the circuit is idle, reading when the data has been requested and writing when updating the contents. The three different states work as follows:
Standby
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines. And the two cross coupled inverters formed by M1- M4 will continue to reinforce each other as long as they are disconnected from the outside world.
Reading
Assume that the content of the memory is a 1, stored at Q. The read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line WL, enabling both the access transistors. The second step occurs when the values stored in Q and Q are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to a logical 0. On the BL side, the transistors M4 and M6 pull the bit line towards Vdd, a logical 1. If the content of the memory was a 0, the opposite would happen and BL would be pulled towards 1 and BL towards 0.
Writing
The start of a write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse to a SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself, so that they can easily override the previous state of the cross-coupled inverters. Careful sizing of the transistors in a SRAM cell is needed to ensure proper operation.
Applications
SRAM is faster than DRAM and is used where speed is the prime requirement such as in CPU caches and router buffers. It is also used for external caches, DRAM burst circuits and in its dual-ported form for digital signal processing circuits. Modern FPGAs contain significant amounts of embedded SRAM.
Slow, low-capacity SRAMs are used where low power consumption and low cost are the most important requirements, as in battery-powered backup RAM. SRAM is less dense than DRAM, due to a more complex internal structure, it is therefore not suitable for high-capacity, low-cost applications such as PC memory.
The power consumption of SRAM varies widely depending on clock speed. Fast SRAM is much more power-hungry than DRAM, and some ICs can consume many watts at full speed. Slow SRAM, such as the battery-powered "CMOS" RAM on PC motherboards, can have a very low power consumption, in the region of a microwatt when sitting idle.
Hobbyists have often preferred using SRAM instead of DRAM, due to the ease of interfacing. SRAM is significantly easier to work with and faster to implement than DRAM. There are no refresh cycles, as required with DRAM. The address and data buses are usually fully accessible, rather than multiplexed. SRAM circuits usually require only power, ground, address/data, and three controls: Chip enable (CE), Write enable (WE) and Output enable (OE).
Small SRAM buffers are commonly found in hard disk, CDROM and CDRW drives, even in mini disc recorders. Usually 64 to 256 kbyte (and more), they buffer track data, which is transferred in chunks instead of direct byte writes. SRAM is both fast to access, and easy to control by a microprocessor (CPU).
Types of SRAM
By transistor type
- Bipolar transistor (not much used now: consumes a lot of power but is very fast)
- CMOS (the most common type)
By function
- Asynchronous: Independent of clock frequency, data-in and data out are controlled by address transition
- Synchronous: All timings are initiated by the clock rise/fall time. Address, data-in and other control signals are associated with the clock signals