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| Company type | Private |
|---|---|
| Headquarters | San Jose, California, United States |
Key people |
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Co-Design Automation, Inc., was a San Jose, CA, based provider of hardware design and verification language simulation products. Co-Design's main development was the language Superlog that eventually became the IEEE HDL standard SystemVerilog. Co-Design was acquired by Synopsys, Inc. in August 2002.
History
[edit]The collaboration that become Co-Design was started in 1995 by Simon Davidmann and Peter Flake working part-time to evolve Hardware Description Language ideas to address limitations in traditional HDL usage for large-scale hardware projects.[1][2][3] During this time there were many other companies competing in language design with Co-Design but Superlog became adopted due to its approach of evolving from the Verilog HDL - the leading design language for digital systems and chips, and solving the evolving new requirements.[4]
The business focus of Co-Design was to build a new language to supersede Verilog HDL and to sell simulation and other tools that supported the language in the same way that Gateway Design had done successfully with Verilog HDL.[4] A key focus was to address the growing need for more efficient verification solutions as hardware designs were getting larger and more complex and Superlog was developed to address this need with many new verification capabilities.[2] The goals were to make the processes of design and verification of digital chips more abstract, efficient and faster to complete.[5]
Founding
[edit]Davidmann and Flake had previously worked together at Brunel University in the early 1980s on the development of one of the first HDLs: HILO and in 1995 started collaboration on Superlog leading to the incorporation of Co-Design in 1997.[3][6]
The founders and early management team included:
- Simon Davidmann, CEO and founder
- Peter Flake, CTO and founder
- James Kenney, Chief Engineer
- Dave Kelf, VP Marketing
- Phil Moorby, VP Engineering
Funding
[edit]While the language and concepts were being firmed up, Davidmann and Flake toured Silicon Valley lining up seed funding from technology innovators and visionaries who understood the need and opportunity and shared the Co-Design vision and strategy.[1][2][7]
Investors in early seed funding rounds starting in 1998 included:
- Andy Bechtolsheim - visionary technologist (who also provided seed funding for Sergey Brin and Larry Page in founding Google)
- David Cheriton - visionary academic
- John Sanguinetti[8][9] - founder and CEO of Chronologic Simulation
- Rajeev Madhavan[10] - founder and CEO of Ambit Design Systems and Magma Design Automation
- Raj Parekh and Raj Singh[11] - of Redwood Ventures[12]
- Rich Davenport[13] - Co-Design Chairman
Later funding rounds included strategic investment from:
Technology and Products
[edit]The main focus of Co-Design was to develop a new language and tools that could support it.[7] The new language, Superlog, was conceived as an extension to Verilog, retaining familiarity while introducing more modern software programming constructs. Specific new additions were: advanced data types beyond simple bit vectors, classes and object-oriented features (e.g., inheritance, methods), high-level testbench constructs that reduced dependence on external verification languages, functional coverage, assertions and constraints to improve verification.[1][2]
To support the new language a very high speed interpreted simulator was created by James Kenney and marketed to early customers.[14] Later Phil Moorby joined the team to develop compiled code techniques and rather then creating a new simulator, these techniques were added to the interpreted simulator continually improving its capabilities and run-time speed.[15][16][17]
Market Reception
[edit]By 2000 there were many other groups attempting to develop, evolve, and promote various more advanced languages for hardware design and verification - these discussion got known as the 'EDA Language War'[18][19] - and Accellera hosted many discussions and committees to consider the different alternatives.[20][1][2] During this time the adoption and success of Superlog was growing due to the go-to-market strategy developed by Simon Davidmann and Dave Kelf to get many early adopters to guide the language development and for the Co-Design engineering team to build high speed simulation - while maintaining Verilog compatibility.[7] By 2002 with the help of Intel[21] and Synopsys, Accellera concluded the 'language wars' by using Co-Design's Superlog donation as the basis for the new language it titled SystemVerilog.[22][23] SystemVerilog became in IEEE standard in 2005.[24]
Acquisition
[edit]In august 2002 Synopsys announced it was acquiring Co-Design and taking ownership of Superlog to accelerate the adoption of the new language and accelerate the Synopsys verification road-map.[25][26]
Legacy
[edit]Co-Design's legacy is its creation of the Superlog language and related strategy to get it adopted and standardized as SystemVerilog for it to become the main language used for design and verification of digital electronics in the 2000s and beyond.
References
[edit]- ^ a b c d Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon (2020-06-12). "Verilog HDL and its ancestors and descendants". Proc. ACM Program. Lang. 4 (HOPL): 87:1–87:90. doi:10.1145/3386337.
- ^ a b c d e "SystemVerilog for Design". SpringerLink. 2006. doi:10.1007/0-387-36495-1. ISBN 978-0-387-33399-1.
- ^ a b Dettmer, R. (2004-08-01). "The HILO inheritance". IEE Review. 50 (8): 22–26. doi:10.1049/ir:20040803 (inactive 29 May 2025). ISSN 0953-5683.
{{cite journal}}: CS1 maint: DOI inactive as of May 2025 (link) - ^ a b EETimes (2000-11-06). "The Superlog evolution". EE Times. Retrieved 2025-05-29.
- ^ "Co-Design Automation Launches Innovative Product Line to Reshape System Design Methodologies". www.design-reuse.com. Retrieved 2025-05-29.
- ^ "Imperas Reunites with SystemVerilog Co-Founders at DVCon 2021". Electronic Design. 2021-02-25. Retrieved 2025-05-29.
- ^ a b c Clarke, Peter (1999-05-31). "Startup to field next-generation design language". EE Times. Retrieved 2025-05-29.
- ^ Sanguinetti, John (1979-08-13). "A technique for integrating simulation and system design". ACM SIGSIM Simulation Digest. 11 (1): 163–172. doi:10.1145/1013608.805457. ISSN 0163-6103.
- ^ Computer History Museum (2016-08-30). Simulation Speed and Logic Design, lecture by John Sanguinetti. Retrieved 2025-05-29 – via YouTube.
- ^ "Rajeev Madhavan – Clear Ventures". clear.ventures. Retrieved 2025-05-29.
- ^ "The fiber Raj". Forbes. Retrieved 2025-05-29.
- ^ a b c "Co-Design Automation Stock Price, Funding, Valuation, Revenue & Financial Statements". www.cbinsights.com. Retrieved 2025-05-29.
- ^ Davenport, Rich (28 May 2025). "Rich Davenport".
- ^ "Co-Design Automation, Inc". Semiconductor Engineering. Retrieved 2025-05-29.
- ^ "Phil Moorby". Semiconductor Engineering. Retrieved 2025-05-29.
- ^ "Phil Moorby: Phil Kaufman Award, 2004". people.eecs.berkeley.edu. Retrieved 2025-05-29.
- ^ "Philip Moorby". CHM. 2025-05-23. Retrieved 2025-05-29.
- ^ "Verilog HDL and Its Ancestors and Descendants - Breakfast Bytes - Cadence Blogs - Cadence Community". community.cadence.com. 2021-03-23. Retrieved 2025-05-29.
- ^ Maliniak, David (2001-10-01). "Design Languages Vie For System-Level Dominance". Electronic Design. Retrieved 2025-05-29.
- ^ EETimes (2000-11-06). "The Superlog evolution". EE Times. Retrieved 2025-05-29.
- ^ "Intel pushes assertion language as EDA standard". www.design-reuse.com. Retrieved 2025-05-29.
- ^ Staff (2001-06-13). "Co-Design Automation confims deal to give Superlog hardware language to Accellera". Electronics Weekly. Retrieved 2025-05-29.
- ^ Cummings, Clifford (11-05-2003). "SystemVerilog - Is This The Merging of Verilog & VHDL?" (PDF). sunburst-design.com/.
{{cite web}}: Check date values in:|date=(help) - ^ Ho, Kaiming (September 2013). "SystemVerilog: The new standard". Proceedings of the 2013 Forum on Specification and Design Languages (FDL): 1.
- ^ "Synopsys Acquires Co-Design Automation to Accelerate Delivery of Next-Generation HDL With SUPERLOG Technology". www.design-reuse.com. Retrieved 2025-05-29.
- ^ Santarini, Mike (2002-08-30). "Superlog deal lets Synopsys C future". EDN. Retrieved 2025-05-29.