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Draft:Peter Flake

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Peter L. Flake is a British computer scientist and electronic‑design‑automation (EDA) engineer best known for creating HILO, one of the first commercial hardware‑description‑language (HDL) simulators, and for co‑architecting Superlog, the language that evolved into SystemVerilog. During a career that has stretched from the 1970s to the 2020s he has moved between academia, start‑ups and large EDA vendors, shaping how engineers specify and verify digital systems.

Early life and education

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Peter Flake holds a Master of Arts (MA) degree in engineering sciences from Cambridge University. He began his career with GEC-Elliot Process Automation in Leicester, UK, before moving to the University of Bradford as an experimental officer to nurture a growing interest in software and then moved to Brunel University as a research engineer, where his interest in computer‑aided-design first took shape.[1][2].

Career

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HILO at Brunel University

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At Brunel, Flake led the team that developed HILO, a language and mixed‑level logic‑simulation program capable of modelling switch‑, gate‑ and register‑transfer‑level behavior[3]. The first public description appeared in IEE Proceedings in 1975[4], and an enhanced HILO-2 was later commercialized by GenRad Inc., making it the earliest HDL‑based simulator to gain a significant industrial user base[1]. Following the technology transfer to GenRad, Inc., in the early 1980s, Flake continued development and support of HILO for the company’s customers in production-test environments[5][2].

Co‑Design Automation, Superlog, and SystemVerilog

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In 1998 Flake co‑founded Co‑Design Automation, Inc. with former colleague Simon Davidmann[6]. Their aim was to create a single language that unified design and verification[7][8]. The result, Superlog, was introduced at ASP‑DAC 2000[9], combining C‑like syntax with Verilog semantics. At Co-Design Flake was CTO and managed the engineering team that included James Kenney who developed the simulators and Phil Moorby focusing on performance. Moorby a Kaufman awardee and Fellow of the Computer History Museum stated Flake was his technical mentor[10][11].

in 2002 Co-Design donated the Superlog language to the Accellera standards body[12] as the basis for SystemVerilog which became adopted and standardized by the IEEE as IEEE‑1800 in 2005[13].

Synopsys acquired Co‑Design in August 2002 for approximately USD 36 million[14] where Flake as a Synopsys Scientist (2003-2005) promoted tool development and commercial adoption of SystemVerilog[15]. This SystemVerilog standard has been widely adopted for digital system and integrated circuit design. Many of the object-oriented and assertion-based verification features originally developed by Flake and showcased in Superlog are now foundational in SystemVerilog testbench methodologies[3][16][14].

Imperas and later work

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After leaving Synopsys Flake became Chief Scientist at processor‑modelling start‑up Imperas Ltd. He retired from that post in 2008,but continued consulting through Elda Technology Ltd. and writing on high‑level hardware description.[2]

In 2021 he joined Phil Moorby and Simon Davidmann in a retrospective panel at DVCon U.S.[17], and co‑authored the HOPL‑IV[18] paper “Verilog HDL and its ancestors and descendants”[19]

Publications

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HOPL-IV paper: Verilog HDL and its ancestors and descendants[3]

ASP-DAC paper: Superlog, a Unified Design Language for System-on-chip[9]

Book: SystemVerilog for Hardware Design and Modeling[16]

See also

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References

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  1. ^ a b Dettmer, R. (2004-08-01). "The HILO inheritance". IEE Review. 50 (8): 22–26. doi:10.1049/ir:20040803 (inactive 18 June 2025). ISSN 0953-5683.{{cite journal}}: CS1 maint: DOI inactive as of June 2025 (link)
  2. ^ a b c Clarke, Peter (2008-03-13). "Imperas chief scientist retires to pursue language interests". EE Times. Retrieved 2025-06-18.
  3. ^ a b c Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon (2020-06-12). "Verilog HDL and its ancestors and descendants". Proceedings of the ACM on Programming Languages. 4 (HOPL): 1–90. doi:10.1145/3386337. ISSN 2475-1421.
  4. ^ Flake, Peter (1975). "A Digital Systems Simulator - HILO". IEE Proceedings. 1 (2): 39–53.
  5. ^ "Peter Flake". Semiconductor Engineering. Retrieved 2025-06-18.
  6. ^ Clarke, Peter (1999-05-31). "Startup to field next-generation design language". EDN. Retrieved 2025-06-18.
  7. ^ Suresh, Bharath (2025-05-31). "Evolution of HDLs - Part 2: Keeping up with Moore's Law". Chip Insights. Retrieved 2025-06-18.
  8. ^ EETimes (2000-11-06). "The Superlog evolution". EE Times. Retrieved 2025-06-18.
  9. ^ a b Davidmann, Simon (200). "Superlog, a Unified Design Language for System-on-chip". Asia and South Pacific Design Automation Conference.
  10. ^ "Philip Moorby". CHM. 2025-06-16. Retrieved 2025-06-18.
  11. ^ "ESD Alliance 2005 Phil Kaufman Award | SEMI". www.semi.org. Retrieved 2025-06-18.
  12. ^ Staff (2001-06-13). "Co-Design Automation confims deal to give Superlog hardware language to Accellera". Electronics Weekly. Retrieved 2025-06-18.
  13. ^ "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language". IEEE STD 1800-2023 (Revision of IEEE STD 1800-2017): 1–1354. 2024-02-02. doi:10.1109/IEEESTD.2024.10458102. ISBN 979-8-8557-0500-3.
  14. ^ a b EETimes (2002-08-28). "Synopsys snaps up Co-Design for Superlog language". EE Times. Retrieved 2025-06-18.
  15. ^ "Synopsys Acquires Co-Design Automation to Accelerate Delivery of Next-Generation HDL With SUPERLOG Technology". www.design-reuse.com. Retrieved 2025-06-18.
  16. ^ a b "SystemVerilog for Design". SpringerLink. 2006. doi:10.1007/0-387-36495-1. ISBN 978-0-387-33399-1.
  17. ^ You, Semiconductor For (2021-02-25). "Imperas reunites with SystemVerilog Co-Founders at DVCon 2021". Semiconductor for You. Retrieved 2025-06-18.
  18. ^ "HOPL IV". hopl4.sigplan.org. Retrieved 2025-06-18.
  19. ^ "Verilog HDL and its ancestors and descendants (HOPL IV - Papers) - HOPL IV". hopl4.sigplan.org. Retrieved 2025-06-18.
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